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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
Patch Set 48:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52800/comment/87ebd14c_54206370
PS48, Line 11:
also adding one line here about the motivation would be helpful why we need this ?
We have hecienable UPD that manages the ME enable/disable using either PMC IPC or SMI SBI, and why this is needed?
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Hello build bot (Jenkins), SRIDHAR SIRICILLA, Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#48).
Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Added .enable method that will set the CSME state.
State is based on me_state, with values of 0 and 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 119 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/48
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Change subject: cpu/intel/common: Add CAR debug Kconfig CPU_CAR_DEBUG
......................................................................
Patch Set 2:
(1 comment)
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/55653/comment/badfd6fa_6889693d
PS2, Line 369: 4ULL * GiB - 64 * KiB
> I guess you are trying to avoid the bootblock here, while you're calling this inside the bootblock?
> Make this explicit?
> 1) Don't run this !ENV_BOOTBLOCK
won't earlier comment will take care of this as well?
Arthur Heymans
Jun 29
Return if not ENV_CACHE_AS_RAM?
> 2) explicitly avoid addresses inside _bootblock/_ebootblock instead of making the hardcoded assumption on a 64K bootblock, which btw is simply not the case anymore in coreboot.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Added .enable method that will set the CSME state.
State is based on me_state, with values of 0 and 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 119 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/45
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Change subject: include/types.h: #include <limits.h>
......................................................................
include/types.h: #include <limits.h>
It makes sense to provide limits.h via the types.h header.
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Change subject: include/types.h: #include <limits.h>
......................................................................
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Change subject: [TESTME] mb/prodrive/hermes: Update HDA codec subvendor ID
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Note that this change will also need to be done for the R04 board variant.
This change effects all variants
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Change subject: ec: Support specific Q events for different models
......................................................................
Set Ready For Review
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