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Change subject: drivers/intel/gma: Restructure Opregion version info code
......................................................................
Patch Set 6:
(3 comments)
File src/drivers/intel/gma/opregion.h:
https://review.coreboot.org/c/coreboot/+/56168/comment/e4a69cae_96bc38e3
PS5, Line 21:
> one tab less?
Done
https://review.coreboot.org/c/coreboot/+/56168/comment/72b429da_34d82009
PS5, Line 25: __packed
> wondering if we need __packed here ? isn't it already 32-bit variable ?
Done
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/56168/comment/307e4ce8_ce9f3890
PS5, Line 262: 0
> how would you take care of INTEL_GMA_OPREGION_2_1 and INTEL_GMA_OPREGION_2_0, can we use those Kconf […]
Accomodated in the next CL Subrata. Updating the minor version based on the Kconfig check.
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Hello build bot (Jenkins), Maulik V Vaghela, Subrata Banik, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56168
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Change subject: drivers/intel/gma: Restructure Opregion version info code
......................................................................
drivers/intel/gma: Restructure Opregion version info code
Define a structure for opregion version information to align
with spec/kernel.
BUG=b:190019970
BRANCH=None
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b
---
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/gma/opregion.h
2 files changed, 18 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/56168/6
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Change subject: soc/intel/alderlake: Add GFx Device ID 0x46a6
......................................................................
Patch Set 1:
(1 comment)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/56026/comment/5e6dca51_5201d59e
PS1, Line 3821: #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6
> They're already in an arbitrary order, that sounds like it should be a separate commit.
Agree Tim...Let me push separate commit to align order for ADL-P Ids atleast.
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Change subject: drivers/usb/acpi: Create function to get PLD information
......................................................................
Patch Set 8:
(1 comment)
File src/drivers/usb/acpi/usb_acpi.c:
https://review.coreboot.org/c/coreboot/+/56024/comment/114da24f_6c7d22fd
PS4, Line 129: static struct acpi_pld pld;
> We can't just remove `static` keyword. […]
Done
We'll pass PLD pointer to function instead keeping context within this function.
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Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Sridhar Siricilla, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00
......................................................................
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00
The headers added are generated as per FSP v2237_00.
Previous FSP version was v2207_01.
Changes Include:
- Add VccInAuxImonIccImax in FspsUpd.h
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h
BUG=b:192199787
BRANCH=None
TEST=Build and boot brya
Change-Id: Ie291204a3fa0b9451c418c84bd40a17ef08a436c
Cq-Depend:chrome-internal:3970327,chrome-internal:3925290
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
2 files changed, 22 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/55896/4
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Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) silicon
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56073/comment/bd0c6f61_5f8a05b8
PS2, Line 7: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) silicon
The headline of the commit message is limited to 72 characters.
https://review.coreboot.org/c/coreboot/+/56073/comment/fbe5cad2_c85138f2
PS2, Line 16: TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if
: not updated.
Please use proper line length.
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