Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56172 )
Change subject: soc/intel/alderlake: Add missing devices to pci_devs.h
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
The QA test failure seems to be a false positive. The error message last seen when booting Linux seems to be a KVM bug.
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Gerrit-Change-Number: 56172
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56207 )
Change subject: soc/intel/skylake: Drop dead `ScanExtGfxForLegacyOpRom`
......................................................................
soc/intel/skylake: Drop dead `ScanExtGfxForLegacyOpRom`
This devicetree option is never set and never used. Drop it.
Change-Id: I9cd4733746849728b2b9f85793eace9191a97f49
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/skylake/chip.h
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56207/1
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index d30547e..d463c3b 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -283,7 +283,6 @@
Display_Switchable,
} PrimaryDisplay;
u8 SkipExtGfxScan;
- u8 ScanExtGfxForLegacyOpRom;
/* GPIO IRQ Route The valid values is 14 or 15*/
u8 GpioIrqSelect;
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Attention is currently required from: Felix Singer, Nico Huber.
Hello Felix Singer, Nico Huber,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/56205
to review the following change.
Change subject: mb/siemens/chili: Drop ineffective `SaGv` setting
......................................................................
mb/siemens/chili: Drop ineffective `SaGv` setting
SaGv is only available on ULT/ULX processors, which use PCH-LP. Given
that the Siemens Chili board selects `SOC_INTEL_CANNONLAKE_PCH_H`, it
does not use ULT/ULX processors, and thus does not support SaGv. Drop
the `SaGv` setting from the devicetrees, as it has no effect.
Change-Id: I5be518cce08206ad149efd1665e44a7111b24202
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/siemens/chili/variants/base/devicetree.cb
M src/mainboard/siemens/chili/variants/chili/devicetree.cb
2 files changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/56205/1
diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb
index ccbe804..81dae2e 100644
--- a/src/mainboard/siemens/chili/variants/base/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb
@@ -2,7 +2,6 @@
chip soc/intel/cannonlake
# FSP configuration
- register "SaGv" = "SaGv_Enabled"
register "RMT" = "0"
register "PchHdaDspEnable" = "0"
diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
index 4416dbf..b4d9970 100644
--- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb
+++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb
@@ -2,7 +2,6 @@
chip soc/intel/cannonlake
# FSP configuration
- register "SaGv" = "SaGv_Enabled"
register "RMT" = "0"
register "PchHdaDspEnable" = "0"
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Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
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