coreboot-gerrit July 2021

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Change in coreboot[master]: console: Allow configuring log level through CBFS
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Marc Jones, Patrick Rudolph. Hello build bot (Jenkins), Greg Edelston, Jakub Czapiga, Paul Menzel, Julius Werner, Angel Pons, Dossym Nurmukhanov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45208 to look at the new patch set (#15). Change subject: console: Allow configuring log level through CBFS ...................................................................... console: Allow configuring log level through CBFS Allow configuring loglevel through CBFS in addition to the compile time default and the (not always available) "CMOS" nvram. In the first stage (usually bootblock), only the compile time default is used (no change to previous behavior) Later stages first look for valid configuration in nvram, then in CBFS and finally use the compile time default: The first usable value is chosen. "Fast" consoles still log at BIOS_DEBUG level or slow console loglevel, whatever is more verbose. With this change a single image can be used both for deployment and testing scenarios with only a dedicated CBFS file modified to toggle (the typically slow) serial console. BUG=b:151346403 BRANCH=none TEST=Taking a Chrome OS config for google/hatch, it behaves as expected with no entry present and both entry states with negligible performance loss. Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/console/init.c 1 file changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45208/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 15 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/cpu/x86/msr: add mca_get_bank_count function
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56183 ) Change subject: include/cpu/x86/msr: add mca_get_bank_count function ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Gerrit-Change-Number: 56183 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 12:41:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{cezanne,common}: Enable IOMMU PCIe Device
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55737 ) Change subject: soc/amd/{cezanne,common}: Enable IOMMU PCIe Device ...................................................................... soc/amd/{cezanne,common}: Enable IOMMU PCIe Device This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/iommu/iommu.c 3 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index cf0f515..30ebe62 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -186,6 +186,8 @@ }" device domain 0 on + device ref iommu on end + device ref gpp_bridge_0 on chip drivers/wifi/generic register "wake" = "GEVENT_8" diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1bb9353..8f93512 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -47,6 +47,7 @@ select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 49683d4..b6e4ac2 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -42,6 +42,7 @@ PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU, + PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/55737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Gerrit-Change-Number: 55737 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{cezanne,common}: Enable IOMMU PCIe Device
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Jason Glenesk. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55737 ) Change subject: soc/amd/{cezanne,common}: Enable IOMMU PCIe Device ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > The way i'm understanding the plumbing, we might need to set this eventually. […] ok -- To view, visit https://review.coreboot.org/c/coreboot/+/55737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Gerrit-Change-Number: 55737 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 12:30:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/x86/msr: fix MCG_CTL_P definition
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56179 ) Change subject: include/cpu/x86/msr: fix MCG_CTL_P definition ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56179/comment/e0642a89_7c7e2ddb PS1, Line 10: that MSR contain the number of MCA banks being present on the CPU. > Please mention that the `MCG_CTL_P` macro is not used anywhere. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Gerrit-Change-Number: 56179 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 12:22:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/x86/msr: fix MCG_CTL_P definition
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Felix Held. Hello build bot (Jenkins), Raul Rangel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56179 to look at the new patch set (#2). Change subject: include/cpu/x86/msr: fix MCG_CTL_P definition ...................................................................... include/cpu/x86/msr: fix MCG_CTL_P definition MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of that MSR contain the number of MCA banks being present on the CPU. At the moment this definition of MCG_CTL_P is unused. Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/x86/msr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/56179/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Gerrit-Change-Number: 56179 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/cpu/x86/msr: add mca_get_bank_count function
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Werner Zeh. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56183 ) Change subject: include/cpu/x86/msr: add mca_get_bank_count function ...................................................................... Patch Set 2: (1 comment) File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/56183/comment/b889a9fb_0fa0a107 PS1, Line 158: get > Get Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Gerrit-Change-Number: 56183 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 12:18:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/x86/msr: add mca_get_bank_count function
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56183 to look at the new patch set (#2). Change subject: include/cpu/x86/msr: add mca_get_bank_count function ...................................................................... include/cpu/x86/msr: add mca_get_bank_count function In multiple locations within the coreboot tree the IA32_MCG_CAP MSR gets read and masked with MCA_BANKS_MASK to get the number of available MCA banks on the CPU, so add this to the common code to avoid duplication of code. Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/x86/msr.h 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/56183/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Gerrit-Change-Number: 56183 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Get DRAM size from DRAM calibration result
by Hung-Te Lin (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56204 ) Change subject: soc/mediatek/mt8195: Get DRAM size from DRAM calibration result ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic34f29d1692b94284b2cf6c5d91d323df736c76f Gerrit-Change-Number: 56204 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 11:56:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Get DRAM size from DRAM calibration result
by Rex-BC Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56204 ) Change subject: soc/mediatek/mt8195: Get DRAM size from DRAM calibration result ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8195/emi.c: https://review.coreboot.org/c/coreboot/+/56204/comment/ea61a56c_73b487ed PS1, Line 10: size_t > I think the sdram_size may be called multiple times in ram stage (also rom stage). […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic34f29d1692b94284b2cf6c5d91d323df736c76f Gerrit-Change-Number: 56204 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 11:48:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit July 2021