coreboot-gerrit July 2021

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Change in coreboot[master]: drivers/intel/gma: Restructure Opregion version info code
by Subrata Banik (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Meera Ravindranath, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56168 ) Change subject: drivers/intel/gma: Restructure Opregion version info code ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/gma/opregion.c: https://review.coreboot.org/c/coreboot/+/56168/comment/d5ef1de1_d2f646f7 PS6, Line 261: 2 > Given that OpRegion versions have subfields, I'd rather fill in the version numbers in C code. […] knowing that, Rev and Rsvd always having 0, can't we use below logic? Thoughts ? union opregion_version { u32 data; struct fields{ u8 rsvd; u8 revision; u8 minor; u8 major; }; }; +---------------+---------------+------+------+------------------+ | 31:24 | 23:16 | 15:8 | 7:0 | Opregion version | +---------------+---------------+------+------+------------------+ | Major Version | Minor version | Rev | Rsvd | | | 1 | 0 | 0 | 0 | 1.0.0 | | 1 | 5 | 0 | 0 | 1.5.0 | | 2 | 3 | 0 | 0 | 2.3.0 | | A | F | 0 | 0 | 10.15 | +---------------+---------------+------+------+------------------+ config OPREGION_2_0_VERSION int default 2000 config OPREGION_2_1_VERSION int default 2100 config OPREGION_3_0_VERSION int default 3000 -- To view, visit https://review.coreboot.org/c/coreboot/+/56168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Gerrit-Change-Number: 56168 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 08:30:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: Restructure Opregion version info code
by Angel Pons (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Angel Pons, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56168 ) Change subject: drivers/intel/gma: Restructure Opregion version info code ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/gma/opregion.c: https://review.coreboot.org/c/coreboot/+/56168/comment/ac0ae211_19a80e34 PS6, Line 261: 2 > if you are interested to use version number generic enough, i would recommend to implement something […] Given that OpRegion versions have subfields, I'd rather fill in the version numbers in C code. Otherwise, we would need to repeat the Kconfig options three times, once for each of the subfields: `major`, `minor`, `revision`. -- To view, visit https://review.coreboot.org/c/coreboot/+/56168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Gerrit-Change-Number: 56168 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 08:18:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: Restructure Opregion version info code
by Subrata Banik (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56168 ) Change subject: drivers/intel/gma: Restructure Opregion version info code ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/gma/opregion.c: https://review.coreboot.org/c/coreboot/+/56168/comment/e22473e0_a9412bd2 PS6, Line 261: 2 if you are interested to use version number generic enough, i would recommend to implement something similar to this https://github.com/coreboot/coreboot/blob/master/src/vendorcode/intel/Kconf… UDK_VERSION => OPREGION_VERSION UDK_2015_VERSION => OPREGION_2_0_VERSION UEFI_2_4_BINDING => INTEL_GMA_OPREGION_2_0 -- To view, visit https://review.coreboot.org/c/coreboot/+/56168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Gerrit-Change-Number: 56168 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 07:58:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma: Restructure Opregion version info code
by Angel Pons (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Angel Pons, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56168 ) Change subject: drivers/intel/gma: Restructure Opregion version info code ...................................................................... Patch Set 6: Code-Review+1 (2 comments) File src/drivers/intel/gma/opregion.h: https://review.coreboot.org/c/coreboot/+/56168/comment/724d6fcf_f27c99e7 PS6, Line 37: #define IGD_OPREGION_VERSION 2 Please drop this macro, it is no longer used. File src/drivers/intel/gma/opregion.c: https://review.coreboot.org/c/coreboot/+/56168/comment/b86a243f_ad7054a0 PS6, Line 259: static void opregion_set_version(opregion_header_t *opheader) Looks like my comment on https://review.coreboot.org/c/coreboot/+/52758/comment/03016642_bb98db26/ was missed: > Another approach is to return a struct, but one needs to expose the struct type: > > struct __packed opregion_version { > u8 rsvd; > u8 revision; > u8 minor; > u8 major; > }; > > One would then declare `over` in the mailbox 0 struct as follows: > > struct opregion_version over; > > And the resulting function would then be: > > static struct opregion_version opregion_get_version(void) > { > return (struct opregion_version) { .major = 2, .minor = 0 }; > } > > This function would then be used as follows: > > opregion->header.over = opregion_get_version(); Thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/56168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Gerrit-Change-Number: 56168 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 07:54:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Angel Pons (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Arthur Heymans, Rocky Phagura, Subrata Banik, Andrey Petrov, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rocky Phagura Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 07:41:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: Add function to simplify If (CondRefOf (..)) sequences
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56003 ) Change subject: acpi: Add function to simplify If (CondRefOf (..)) sequences ...................................................................... acpi: Add function to simplify If (CondRefOf (..)) sequences The new function is called acpigen_write_if_cond_refof(), and it must be paired with a following acpigen_write_if_end() call. Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56003 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 9818dc2..8320b6c 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1501,6 +1501,21 @@ acpigen_write_integer(val); } +/* + * Generates ACPI code to check at runtime if an object named `namestring` + * exists, and leaves the If scope open to continue execute code when this + * is true. NOTE: Requires matching acpigen_write_if_end(). + * + * If (CondRefOf (NAME)) + */ +void acpigen_write_if_cond_ref_of(const char *namestring) +{ + acpigen_write_if(); + acpigen_emit_ext_op(COND_REFOF_OP); + acpigen_emit_namestring(namestring); + acpigen_emit_byte(ZERO_OP); /* ignore COND_REFOF_OP destination */ +} + /* Closes previously opened if statement and generates ACPI code for else statement. */ void acpigen_write_else(void) { diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 2d0bb77..09ec4bc 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -415,6 +415,8 @@ { acpigen_pop_len(); } +/* Emits If (CondRefOf(NAME)) */ +void acpigen_write_if_cond_ref_of(const char *namestring); void acpigen_write_else(void); void acpigen_write_shiftleft_op_int(uint8_t src_result, uint64_t count); void acpigen_write_to_buffer(uint8_t src, uint8_t dst); -- To view, visit https://review.coreboot.org/c/coreboot/+/56003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Gerrit-Change-Number: 56003 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: acpi: Add function to simplify If (CondRefOf (..)) sequences
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Cliff Huang, Furquan Shaikh, Angel Pons, Michael Niewöhner, Karthik Ramasubramanian. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56003 ) Change subject: acpi: Add function to simplify If (CondRefOf (..)) sequences ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Gerrit-Change-Number: 56003 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 07:33:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/sb800: Cast to UINT32 for shift out of bounds fix
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51284 ) Change subject: vc/amd/sb800: Cast to UINT32 for shift out of bounds fix ...................................................................... vc/amd/sb800: Cast to UINT32 for shift out of bounds fix It’s defined as `unsigned char`. SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:643:53 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I0c5fa16bce5b68ed3b48bb17eae6d81af894b688 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51284 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/vendorcode/amd/cimx/sb800/SBCMN.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index 8f1bbf9..3d4ce82 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -640,12 +640,12 @@ while ( (pABTbl->regType) != 0xFF ) { if ( pABTbl->regType > AXINDC ) { - ddValue = pABTbl->regIndex | (pABTbl->regType << 29); + ddValue = pABTbl->regIndex | ((UINT32) pABTbl->regType << 29); writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); } else { - ddValue = 0x30 | (pABTbl->regType << 29); + ddValue = 0x30 | ((UINT32) pABTbl->regType << 29); writeAlink (ddValue, pABTbl->regIndex); - ddValue = 0x34 | (pABTbl->regType << 29); + ddValue = 0x34 | ((UINT32) pABTbl->regType << 29); writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); } ++pABTbl; -- To view, visit https://review.coreboot.org/c/coreboot/+/51284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c5fa16bce5b68ed3b48bb17eae6d81af894b688 Gerrit-Change-Number: 51284 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/amd/sb800: Cast variable to 32-bit before shift
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51285 ) Change subject: vc/amd/sb800: Cast variable to 32-bit before shift ...................................................................... vc/amd/sb800: Cast variable to 32-bit before shift SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/Gpp.c:151:61 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: I6cbef2fa9806fd6da67031ca01bb25205013b478 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51285 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/vendorcode/amd/cimx/sb800/Gpp.c 1 file changed, 44 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/vendorcode/amd/cimx/sb800/Gpp.c b/src/vendorcode/amd/cimx/sb800/Gpp.c index ae7f3ce..e7ff2ea 100644 --- a/src/vendorcode/amd/cimx/sb800/Gpp.c +++ b/src/vendorcode/amd/cimx/sb800/Gpp.c @@ -137,28 +137,28 @@ if ( cimAlinkPhyPllPowerDown == TRUE ) { UINT32 abValue; // Set PCIE_P_CNTL in Alink PCIEIND space - writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40); - abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29)); + writeAlink (SB_AX_INDXC_REG30 | ((UINT32) AXINDC << 29), 0x40); + abValue = readAlink (SB_AX_DATAC_REG34 | ((UINT32) AXINDC << 29)); abValue |= BIT12 + BIT3 + BIT0; abValue &= ~(BIT9 + BIT4); - writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue); - rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~BIT8, (BIT8)); + writeAlink (SB_AX_DATAC_REG34 | ((UINT32) AXINDC << 29), abValue); + rwAlink (SB_AX_INDXC_REG02 | ((UINT32) AXINDC << 29), ~BIT8, (BIT8)); } // // Set ABCFG 0x031C[0] = 1 enable the lane reversal support. // - reg32Value = readAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29)); + reg32Value = readAlink (SB_ABCFG_REG31C | ((UINT32) ABCFG << 29)); if ( cimGppLaneReversal ) { - writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | BIT0); + writeAlink (SB_ABCFG_REG31C | ((UINT32) ABCFG << 29), reg32Value | BIT0); } else { - writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | 0x00); + writeAlink (SB_ABCFG_REG31C | ((UINT32) ABCFG << 29), reg32Value | 0x00); } // // Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function // - reg32Value = readAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)); - writeAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), reg32Value | BIT20); + reg32Value = readAlink (SB_ABCFG_REG90 | ((UINT32) ABCFG << 29)); + writeAlink (SB_ABCFG_REG90 | ((UINT32) ABCFG << 29), reg32Value | BIT20); // @@ -173,14 +173,14 @@ // GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4 // if ( cimGppMemWrImprove == TRUE ) { - rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26)); - rwAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12)); + rwAlink (SB_ABCFG_REG54 | ((UINT32) ABCFG << 29), ~BIT26, (BIT26)); + rwAlink (SB_RCINDXC_REG10 | ((UINT32) RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12)); } if ( pConfig->S3Resume ) { for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { - reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29)); - writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21); + reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29)); + writeAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29), reg32Value & ~BIT21); } } // @@ -202,8 +202,8 @@ // Check failure port and clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { if (TogglePort & (1 << portNum)) { - reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29)); - writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21); + reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29)); + writeAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29), reg32Value & ~BIT21); } sbGppForceGen1 (portNum); } @@ -229,13 +229,13 @@ // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF // ABCFG 0xC0[7:4] = 0x0 - rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, (BIT4 + BIT5 + BIT6 + BIT7)); - rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, (BIT12 + BIT13 + BIT14 + BIT15)); + rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), ~BIT8, (BIT4 + BIT5 + BIT6 + BIT7)); + rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), 0xFFFFFFFF, (BIT12 + BIT13 + BIT14 + BIT15)); rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); - rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); + rwAlink ((SB_ABCFG_REG90 | ((UINT32) ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, 0x0fffffff); - rwAlink ((SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)), ~(BIT4 + BIT5 + BIT6 + BIT7), 0); + rwAlink ((SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)), ~(BIT4 + BIT5 + BIT6 + BIT7), 0); } sbGppDisableUnusedPadMap ( pConfig ); } @@ -304,10 +304,10 @@ // tmp16Value = (UINT16) (~reg32Value << 12); reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode); - writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), reg32Value); + writeAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), reg32Value); - reg32Value = readAlink (0xC0 | (UINT32) (RCINDXC << 29)); - writeAlink (0xC0 | (UINT32) (RCINDXC << 29), reg32Value | 0x400); // Set STRAP_F0_MSI_EN + reg32Value = readAlink (0xC0 | ((UINT32) RCINDXC << 29)); + writeAlink (0xC0 | ((UINT32) RCINDXC << 29), reg32Value | 0x400); // Set STRAP_F0_MSI_EN // A-Link L1 Entry Delay Shortening // AXINDP_Reg 0xA0[7:4] = 0x3 @@ -373,7 +373,7 @@ // // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) // - abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + abIndex = SB_RCINDXP_REGA5 | ((UINT32) RCINDXP << 29) | (portId << 24); Data32 = readAlink (abIndex) & 0x3F; if ((UINT8) (Data32) > 4) { portScanMap2 &= ~(1 << portId); // This port is not empty @@ -397,7 +397,7 @@ // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) // SbStall (1000); // Delay 400us - abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + abIndex = SB_RCINDXP_REGA5 | ((UINT32) RCINDXP << 29) | (portId << 24); Data32 = readAlink (abIndex) & 0x3F3F3F3F; if ( (UINT8) (Data32) == 0x10 ) { @@ -485,7 +485,7 @@ i = 500; Data32 = 0; while ( --i ) { - abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24); + abIndex = SB_RCINDXP_REGA5 | ((UINT32) RCINDXP << 29) | (portId << 24); Data32 = readAlink (abIndex) & 0x3F; if ((UINT8) (Data32) == 0x10) { break; @@ -514,7 +514,7 @@ // Status = AGESA_SUCCESS; pConfig->GppFoundGfxDev = 0; - abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + abValue = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { portCfg = &pConfig->PORTCONFIG[portId].PortCfg; @@ -541,7 +541,7 @@ } // Clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) to make hotplug working if ( portCfg->PortHotPlug == TRUE ) { - rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0); + rwAlink ((SB_ABCFG_REG340 + portId * 4) | ((UINT32) ABCFG << 29), ~BIT21, 0); // RPR5.12 Hot Plug: PCIe Native Support // RCINDP_Reg 0x10[3] = 0x1 @@ -549,10 +549,10 @@ // PCIe_Cfg 0x6C[6] = 0x1 // RCINDP_Reg 0x20[19] = 0x0 - rwAlink ((SB_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3); + rwAlink ((SB_RCINDXP_REG10 | ((UINT32) RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3); RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0); RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6); - rwAlink ((SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24)), ~BIT19, 0); + rwAlink ((SB_RCINDXP_REG20 | ((UINT32) RCINDXP << 29) | (portId << 24)), ~BIT19, 0); } } if ( pConfig->GppUnhidePorts == FALSE ) { @@ -563,7 +563,7 @@ } // Update GPP_Portx_Enable (abcfg:0xC0[7:5]) - writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue); + writeAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), abValue); } // @@ -578,12 +578,12 @@ WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue); // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 - abIndex = SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (portId << 24); + abIndex = SB_RCINDXP_REG70 | ((UINT32) RCINDXP << 29) | (portId << 24); abValue = readAlink (abIndex) | BIT19; writeAlink (abIndex, abValue); // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 - abIndex = SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24); + abIndex = SB_RCINDXP_REG20 | ((UINT32) RCINDXP << 29) | (portId << 24); abValue = readAlink (abIndex) & ~BIT19; writeAlink (abIndex, abValue); @@ -615,7 +615,7 @@ // // Configure ASPM // -// writeAlink (0xC0 | (UINT32) (RCINDXC << 29), 0x400); // Set STRAP_F0_MSI_EN +// writeAlink (0xC0 | ((UINT32) RCINDXC << 29), 0x400); // Set STRAP_F0_MSI_EN aspmValue = (UINT8)pConfig->GppPortAspm; cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown; #if SB_CIMx_PARAMETER == 0 @@ -644,10 +644,10 @@ // // Configure Lock HWInit registers // - reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + reg32Value = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); if (reg32Value & 0xF0) { - reg32Value = readAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29)); - writeAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), reg32Value | BIT0); // Set HWINIT_WR_LOCK + reg32Value = readAlink (SB_RCINDXC_REG10 | ((UINT32) RCINDXC << 29)); + writeAlink (SB_RCINDXC_REG10 | ((UINT32) RCINDXC << 29), reg32Value | BIT0); // Set HWINIT_WR_LOCK if ( cimGppPhyPllPowerDown == TRUE ) { // @@ -655,22 +655,22 @@ // UINT32 abValue; // Set PCIE_P_CNTL in Alink PCIEIND space - abValue = readAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29)); + abValue = readAlink (RC_INDXC_REG40 | ((UINT32) RCINDXC << 29)); abValue |= BIT12 + BIT3 + BIT0; abValue &= ~(BIT9 + BIT4); - writeAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), abValue); + writeAlink (RC_INDXC_REG40 | ((UINT32) RCINDXC << 29), abValue); } } // // Configure Lock HWInit registers // - reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + reg32Value = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); // // Disable hidden register decode and serial number capability // - reg32Value = readAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29)); - writeAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29), reg32Value & ~(BIT26 + BIT10)); + reg32Value = readAlink (SB_ABCFG_REG330 | ((UINT32) ABCFG << 29)); + writeAlink (SB_ABCFG_REG330 | ((UINT32) ABCFG << 29), reg32Value & ~(BIT26 + BIT10)); } /** @@ -890,11 +890,11 @@ // ABCFG 0xC0[7:4] = 0x0 if ( (Data32 & 0xf) == 0xf ) Data32 |= 0x0cff0000; if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) { - rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, 0); - rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, HoldData32); + rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), ~BIT8, 0); + rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), 0xFFFFFFFF, HoldData32); rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); - rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); + rwAlink ((SB_ABCFG_REG90 | ((UINT32) ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, Data32); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/51285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cbef2fa9806fd6da67031ca01bb25205013b478 Gerrit-Change-Number: 51285 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/amd/sb800: SBCMN: Cast to 32-bit before shift
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51286 ) Change subject: vc/amd/sb800: SBCMN: Cast to 32-bit before shift ...................................................................... vc/amd/sb800: SBCMN: Cast to 32-bit before shift SB800: sb_Before_Pci_Init shift out of bounds src/vendorcode/amd/cimx/sb800/SBCMN.c:486:57 ubsan: unrecoverable error. Found-by: UBSAN Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51286 Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/amd/cimx/sb800/SBCMN.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index ab203a1..8f1bbf9 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -417,9 +417,9 @@ abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers // AB MSI if ( pConfig->BuildParameters.AbMsi) { - abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29)); + abValue = readAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29)); abValue = abValue | BIT20; - writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue); + writeAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29), abValue); } @@ -483,12 +483,12 @@ ) { UINT32 abValue; - abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)); + abValue = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); abValue &= 0xf0; if ( pConfig->SbPcieOrderRule && abValue ) { - abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)); + abValue = readAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29)); abValue = abValue | BIT9; - writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue); + writeAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29), abValue); } } @@ -620,7 +620,7 @@ pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]); abcfgTbl (pAbTblPtr); if ( cimResetCpuOnSyncFlood ) { - rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2); + rwAlink (SB_ABCFG_REG10050 | ((UINT32) ABCFG << 29), ~BIT2, BIT2); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/51286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id05b96f1f4cf4a1cf8283db22e10ab8df833406d Gerrit-Change-Number: 51286 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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