coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/generic/ioapic: Drop enable_virtual_wire
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Stefan Ott, Furquan Shaikh, Kyösti Mälkki, Alexander Couzens, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55287 ) Change subject: drivers/generic/ioapic: Drop enable_virtual_wire ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55287/comment/ea1ad926_c17ee6be PS2, Line 7: arch/x86/ioapic > That's sort of the WIP question there, should this extend to all mainboards or selected chipsets. […] Ack https://review.coreboot.org/c/coreboot/+/55287/comment/738d1cf9_db48ca8c PS2, Line 9: noapic > The test I was planning is to run OS in legacy i8259 interrupt mode, with both IOAPIC and LAPIC hard […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/55287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93 Gerrit-Change-Number: 55287 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 07:31:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/usb4/retimer: remove redundant structure member group(PLD)
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56025 ) Change subject: drivers/intel/usb4/retimer: remove redundant structure member group(PLD) ...................................................................... drivers/intel/usb4/retimer: remove redundant structure member group(PLD) Currently, we get PLD information from USB port structure itself, so devicetree does not need to fill PLD structure anymore. Thus remove obsolete variable. Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/usb4/retimer/chip.h 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h index 46bd77a..cb01f18 100644 --- a/src/drivers/intel/usb4/retimer/chip.h +++ b/src/drivers/intel/usb4/retimer/chip.h @@ -14,8 +14,6 @@ struct { /* GPIO used to control power of retimer device */ struct acpi_gpio power_gpio; - /* _PLD setting */ - struct acpi_pld_group group; /* Type-C port associated with retimer */ DEVTREE_CONST struct device *typec_port; } dfp[DFP_NUM_MAX]; -- To view, visit https://review.coreboot.org/c/coreboot/+/56025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a561677ab65ddb870d1b00b35ee9d7a22ef9c70 Gerrit-Change-Number: 56025 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya,primus,voxel: Update controller field for tbt_dma entries
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55946 ) Change subject: mb/google/brya,primus,voxel: Update controller field for tbt_dma entries ...................................................................... mb/google/brya,primus,voxel: Update controller field for tbt_dma entries We need to reference correct USB port number for driver to identify type-C port number correctly. BUG=b:189476816 BRANCH=None TEST=Check the transactions are happening on correct port. Also checked retimer firmware update on both the ports. Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55946 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 3 files changed, 12 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 9584b27..eb0af99 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -165,17 +165,15 @@ end device ref tcss_dma0 on chip drivers/intel/usb4/retimer - register "dfp" = "{ - [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), - .group = ACPI_PLD_GROUP(1, 1),}}" + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer - register "dfp" = "{ - [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), - .group = ACPI_PLD_GROUP(3, 1)}}" + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port device generic 0 on end end end diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 36d015d..2d68c36 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -158,17 +158,15 @@ end #PCIE3 BH799BB device ref tcss_dma0 on chip drivers/intel/usb4/retimer - register "dfp" = "{ - [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), - .group = ACPI_PLD_GROUP(1, 1),}}" + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer - register "dfp" = "{ - [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4), - .group = ACPI_PLD_GROUP(3, 1)}}" + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port device generic 0 on end end end diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index b3619b2..7eabfa4 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -220,11 +220,10 @@ probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 chip drivers/intel/usb4/retimer - register "dfp" = "{ - [0] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10), - .group = ACPI_PLD_GROUP(3, 2),}, - [1] = {.power_gpio = ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10), - .group = ACPI_PLD_GROUP(2, 2),}}" + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H10)" + use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[1].typec_port device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/55946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c088ee81610155067abad086eba8d72f73ad60 Gerrit-Change-Number: 55946 Gerrit-PatchSet: 13 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/usb4/retimer: Update code to assign correct port number
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55945 ) Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number ...................................................................... drivers/intel/usb4/retimer: Update code to assign correct port number Since TBT controller can have maximum 2 ports per controller, our code will loop over DFP structure twice and determine port number. Retimer driver used to assign port number as below: 1. Check if power GPIO is assigned for particular DFP entry or not 2. If entry is there, assign loop count as port number Since loop count is 2, retimer will never assign port number = 2 even if it's present. In case of more than 1 controller, port number assigned will still be 0 or 1 even though actual port index might be 2 or 3. This will create an issue where even if you do transaction on device on controller 2 (port index 2 or 3), EC will route it on port 0 or 1 due to incorrect port index. Update the driver flow as per below to handle this scenario: 1. Check if power GPIO is assigned for particular DFP entry or not 2. Get USB port number from config since it's stored in usb port information under devicetree 3. Pass the port number to ACPI SSDT and EC code Above changes will ensure that we're assigning correct port number as per calculation and EC will use correct port index. BUG=b:189476816 BRANCH=None TEST=Checked that retimer firmware update works on both ports and update happens on correct port index. Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55945 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/usb4/retimer/chip.h M src/drivers/intel/usb4/retimer/retimer.c 2 files changed, 24 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/usb4/retimer/chip.h b/src/drivers/intel/usb4/retimer/chip.h index 5b1c76f..46bd77a 100644 --- a/src/drivers/intel/usb4/retimer/chip.h +++ b/src/drivers/intel/usb4/retimer/chip.h @@ -16,6 +16,8 @@ struct acpi_gpio power_gpio; /* _PLD setting */ struct acpi_pld_group group; + /* Type-C port associated with retimer */ + DEVTREE_CONST struct device *typec_port; } dfp[DFP_NUM_MAX]; }; diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c index e84d29b..e549525 100644 --- a/src/drivers/intel/usb4/retimer/retimer.c +++ b/src/drivers/intel/usb4/retimer/retimer.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <device/device.h> #include <device/path.h> +#include <drivers/usb/acpi/chip.h> #include <gpio.h> #include <string.h> #include "chip.h" @@ -336,9 +337,10 @@ static void usb4_retimer_fill_ssdt(const struct device *dev) { struct drivers_intel_usb4_retimer_config *config = dev->chip_info; + const struct device *usb_device; static char dfp[DEVICE_PATH_MAX]; struct acpi_pld pld; - uint8_t port; + uint8_t dfp_port, usb_port; usb4_retimer_scope = acpi_device_scope(dev); if (!usb4_retimer_scope || !config) @@ -352,24 +354,31 @@ acpigen_write_ADR(0); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); - for (port = 0; port < DFP_NUM_MAX; port++) { - if (!config->dfp[port].power_gpio.pin_count) { - printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n", __func__, - port, dev_path(dev)); + for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) { + + if (!config->dfp[dfp_port].power_gpio.pin_count) { + printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n", + __func__, dfp_port, dev_path(dev)); continue; } + usb_device = config->dfp[dfp_port].typec_port; + usb_port = usb_device->path.usb.port_id; + /* DFPx */ - snprintf(dfp, sizeof(dfp), "DFP%1d", port); + snprintf(dfp, sizeof(dfp), "DFP%1d", usb_port); acpigen_write_device(dfp); /* _ADR part is for the lane adapter */ - acpigen_write_ADR(port*2 + 1); + acpigen_write_ADR(dfp_port*2 + 1); /* Fill _PLD with the same USB 3.x object on the Type-C connector */ - acpi_pld_fill_usb(&pld, UPC_TYPE_PROPRIETARY, &config->dfp[port].group); - pld.shape = PLD_SHAPE_OVAL; - pld.visible = 1; - acpigen_write_pld(&pld); + if (CONFIG(DRIVERS_USB_ACPI)) { + if (usb_acpi_get_pld(usb_device, &pld)) + acpigen_write_pld(&pld); + else + printk(BIOS_ERR, "Error retrieving PLD for USB Type-C %d\n", + usb_port); + } /* Power online reference counter(_PWR) */ acpigen_write_name("PWR"); @@ -387,9 +396,9 @@ /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_pop_len(); - usb4_retimer_write_dsm(port, INTEL_USB4_RETIMER_DSM_UUID, + usb4_retimer_write_dsm(usb_port, INTEL_USB4_RETIMER_DSM_UUID, usb4_retimer_callbacks, ARRAY_SIZE(usb4_retimer_callbacks), - (void *)&config->dfp[port].power_gpio); + (void *)&config->dfp[dfp_port].power_gpio); /* Default case: Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); -- To view, visit https://review.coreboot.org/c/coreboot/+/55945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11637ae39046e0afdacd33bc34e8a59e6f2bfb1 Gerrit-Change-Number: 55945 Gerrit-PatchSet: 14 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/usb/acpi: Create function to get PLD information
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56024 ) Change subject: drivers/usb/acpi: Create function to get PLD information ...................................................................... drivers/usb/acpi: Create function to get PLD information Create a separate function to get PLD information from USB device. This is helpful in retimer driver where we can attach same USB port information to retimer instance and we can avoid duplication of information. BUG=None BRANCH=None TEST=Check if code compiles and function returns correct value Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56024 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 23 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 73c69cc..41481f1 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -68,4 +68,7 @@ struct acpi_gpio privacy_gpio; }; +/* Method to get PLD structure from USB device */ +bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld); + #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 9d68d0a..a0dadff 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -37,6 +37,7 @@ { struct drivers_usb_acpi_config *config = dev->chip_info; const char *path = acpi_device_path(dev); + struct acpi_pld pld; if (!path || !config) return; @@ -50,15 +51,10 @@ acpigen_write_name_string("_DDN", config->desc); acpigen_write_upc(config->type); - if (config->use_custom_pld) { - /* Use board defined PLD */ - acpigen_write_pld(&config->custom_pld); - } else { - /* Fill PLD strucutre based on port type */ - struct acpi_pld pld; - acpi_pld_fill_usb(&pld, config->type, &config->group); + if (usb_acpi_get_pld(dev, &pld)) acpigen_write_pld(&pld); - } + else + printk(BIOS_ERR, "Error retrieving PLD for %s\n", path); /* Resources */ if (usb_acpi_add_gpios_to_crs(config) == true) { @@ -126,3 +122,19 @@ CHIP_NAME("USB ACPI Device") .enable_dev = usb_acpi_enable }; + +bool usb_acpi_get_pld(const struct device *usb_device, struct acpi_pld *pld) +{ + struct drivers_usb_acpi_config *config = usb_device->chip_info; + + if (!usb_device || !usb_device->chip_info || + usb_device->chip_ops != &drivers_usb_acpi_ops) + return false; + + if (config->use_custom_pld) + memcpy(pld, &config->custom_pld, sizeof(pld)); + else + acpi_pld_fill_usb(pld, config->type, &config->group); + + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7 Gerrit-Change-Number: 56024 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Abhijeet Rao <abhijeet.rao(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/kukui: Add a new config 'Munna'
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56169 ) Change subject: mb/google/kukui: Add a new config 'Munna' ...................................................................... mb/google/kukui: Add a new config 'Munna' Introduce a new board 'Munna' to Kukui family. BUG=None TEST=make # select Munna BRANCH=kukui Signed-off-by: Sunway <lisunwei(a)huaqin.corp-partner.google.com> Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56169 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 8ba3d46..97b6fed 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -62,6 +62,7 @@ default "Katsu" if BOARD_GOOGLE_KATSU default "Cozmo" if BOARD_GOOGLE_COZMO default "Makomo" if BOARD_GOOGLE_MAKOMO + default "Munna" if BOARD_GOOGLE_MUNNA config DRIVER_TPM_SPI_BUS hex @@ -77,7 +78,7 @@ config BOARD_SDRAM_TABLE_OFFSET hex - default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_MAKOMO + default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_MAKOMO || BOARD_GOOGLE_MUNNA default 0x20 if BOARD_GOOGLE_KAKADU || BOARD_GOOGLE_KATSU default 0x30 if BOARD_GOOGLE_COZMO default 0x0 diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index a6fe60d..6b5b4ce 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -73,3 +73,7 @@ config BOARD_GOOGLE_MAKOMO bool "-> Makomo" select BOARD_GOOGLE_JACUZZI_COMMON + +config BOARD_GOOGLE_MUNNA + bool "-> Munna" + select BOARD_GOOGLE_JACUZZI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/56169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d Gerrit-Change-Number: 56169 Gerrit-PatchSet: 5 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/kukui: Add a new config 'Munna'
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Sunwei Li, Yu-Ping Wu. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56169 ) Change subject: mb/google/kukui: Add a new config 'Munna' ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/kukui/Kconfig: https://review.coreboot.org/c/coreboot/+/56169/comment/619395f7_a229cbf1 PS4, Line 81: default 0x10 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE || BOARD_GOOGLE_FENNEL || BOARD_GOOGLE_CERISE || BOARD_GOOGLE_STERN || BOARD_GOOGLE_MAKOMO || BOARD_GOOGLE_MUNNA not for this commit, but as a potential clean-up opportunity: If the expectation is that most boards need 0x10 here, with a few enumerated outliers, it's possible to "default 0x10" last in this enumeration to make it a default value. See what BOARD_OVERRIDE_LCM_ID below does. -- To view, visit https://review.coreboot.org/c/coreboot/+/56169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie53750d0b79fe6d7c6e7778ba4616b557708601d Gerrit-Change-Number: 56169 Gerrit-PatchSet: 4 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 07:29:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
by Sridhar Siricilla (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Sridhar Siricilla, Rizwan Qureshi, Werner Zeh. Hello build bot (Jenkins), Sridhar Siricilla, Tim Wawrzynczak, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56073 to look at the new patch set (#4). Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon ...................................................................... mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is enabled on the system. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 --- M src/mainboard/intel/adlrvp/bootblock.c 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56073/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Gerrit-Change-Number: 56073 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
by Sridhar Siricilla (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Sridhar Siricilla, Rizwan Qureshi, Werner Zeh. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56073 ) Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56073/comment/4dd422ba_e0051b0e PS2, Line 7: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) silicon > The headline of the commit message is limited to 72 characters. Ack https://review.coreboot.org/c/coreboot/+/56073/comment/4f7200bf_d6c935c5 PS2, Line 16: TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if : not updated. > Please use proper line length. Ack File src/mainboard/intel/adlrvp/bootblock.c: https://review.coreboot.org/c/coreboot/+/56073/comment/49216766_2647305a PS1, Line 5: #include <console/console.h> > We do sort our include in an alphabetical order. Ack https://review.coreboot.org/c/coreboot/+/56073/comment/9f98cab8_d1d4f71c PS1, Line 9: include <console/console.h> > This include is already there on line 5. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Gerrit-Change-Number: 56073 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 07:00:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
by Sridhar Siricilla (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Sridhar Siricilla, Rizwan Qureshi. Hello build bot (Jenkins), Sridhar Siricilla, Tim Wawrzynczak, Rizwan Qureshi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56073 to look at the new patch set (#3). Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon ...................................................................... mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is enableda on the system. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 --- M src/mainboard/intel/adlrvp/bootblock.c 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56073/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Gerrit-Change-Number: 56073 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021