coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/alderlake: Implement WA for DDR5 DIMM modules
by Meera Ravindranath (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Bora Guvendik, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Angel Pons, Patrick Rudolph. Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50996 to look at the new patch set (#22). Change subject: soc/intel/alderlake: Implement WA for DDR5 DIMM modules ...................................................................... soc/intel/alderlake: Implement WA for DDR5 DIMM modules The coreboot SMBus driver requires additional changes to accomodate the DDR5 EEPROM read which has resulted in a broken code flow for boot. This CL serves as a temp WA to let FSP perform the SPD read for DDR5 and pass SPD addresses to FSP UPD array. BUG=b:180458099 TEST=Build and boot DDR5 adlrvp to OS Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a --- M src/soc/intel/alderlake/meminit.c 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/50996/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/50996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Gerrit-Change-Number: 50996 Gerrit-PatchSet: 22 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Update generic device number for mipi_camera device
by Varshit B Pandya (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, Werner Zeh. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56162 ) Change subject: mb/google/brya: Update generic device number for mipi_camera device ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56162/comment/2eaec080_3a624a98 PS1, Line 9: device > devices Done https://review.coreboot.org/c/coreboot/+/56162/comment/ed4c6867_26a2f9c6 PS1, Line 9: overrites > overrides Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a Gerrit-Change-Number: 56162 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 04:41:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update generic device number for mipi_camera device
by Varshit B Pandya (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik. Hello build bot (Jenkins), Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56162 to look at the new patch set (#2). Change subject: mb/google/brya: Update generic device number for mipi_camera device ...................................................................... mb/google/brya: Update generic device number for mipi_camera device If two generic devices use the same number, device coming later overrides the earlier device, as a result of this the static.c has only one device. In the case where we have UFC set to UFC_USB, this will result in no IPU device scope in SSDT, since its entry will be set to disbled after UFC probe. TEST=Build, Boot and Check UFC camera preview with UFC=UFC_USB Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/56162/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a Gerrit-Change-Number: 56162 Gerrit-PatchSet: 2 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/cpu/x86/msr: add mca_get_bank_count function
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56183 ) Change subject: include/cpu/x86/msr: add mca_get_bank_count function ...................................................................... Patch Set 1: (1 comment) File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/56183/comment/13780400_6ba7fd69 PS1, Line 158: get Get -- To view, visit https://review.coreboot.org/c/coreboot/+/56183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Gerrit-Change-Number: 56183 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 04:38:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56193 ) Change subject: soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB ...................................................................... soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Test=Boot ADLRVP and check cbmem -c | grep 'CBFS: Found' lists all stages. Change-Id: I38fd74c2edd71ce9f6c08db9dacb18e553745877 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56193 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4cb512a..778d8a3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -262,7 +262,7 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex - default 0x1400 + default 0x2000 config FSP_HEADER_PATH string "Location of FSP headers" -- To view, visit https://review.coreboot.org/c/coreboot/+/56193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38fd74c2edd71ce9f6c08db9dacb18e553745877 Gerrit-Change-Number: 56193 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56177 ) Change subject: soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared ...................................................................... soc/amd/cezanne/acpi: Change GPIO controller interrupt to shared The Majolica UEFI ACPI tables have this listed as shared. It's already a level interrupt, so no reason it shouldn't be shared. This change makes it so Windows can correctly initialize the GPIO controller. BUG=b:186212501 TEST=Boot guybrush to windows and see GPIO controller functional. Also boot guybrush to windows and verify GPIO controller still works. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/acpi/mmio.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/acpi/mmio.asl b/src/soc/amd/cezanne/acpi/mmio.asl index 7b49b85..6126843 100644 --- a/src/soc/amd/cezanne/acpi/mmio.asl +++ b/src/soc/amd/cezanne/acpi/mmio.asl @@ -34,7 +34,7 @@ ResourceConsumer, Level, ActiveLow, - Exclusive, , , IRQR) + Shared, , , IRQR) { 0 } Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400) } -- To view, visit https://review.coreboot.org/c/coreboot/+/56177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2 Gerrit-Change-Number: 56177 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/irq: Program IRQ pin in irq_program_non_pch()
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56174 ) Change subject: soc/intel/common/irq: Program IRQ pin in irq_program_non_pch() ...................................................................... soc/intel/common/irq: Program IRQ pin in irq_program_non_pch() Previously, irq_program_non_pch() was only programming the IRQ line, but the pin is required as well. BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56174 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/irq/irq.c 1 file changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index f0892a9..00aff62 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -418,10 +418,12 @@ continue; } - if (entry->irq) - pci_s_write_config8(PCI_DEV(0, PCI_SLOT(entry->devfn), - PCI_FUNC(entry->devfn)), - PCI_INTERRUPT_LINE, entry->irq); + if (entry->irq) { + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(entry->devfn), + PCI_FUNC(entry->devfn)); + pci_s_write_config8(dev, PCI_INTERRUPT_LINE, entry->irq); + pci_s_write_config8(dev, PCI_INTERRUPT_PIN, (uint8_t)entry->pin); + } entry = entry->next; } -- To view, visit https://review.coreboot.org/c/coreboot/+/56174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a2823c183a3495721a912de285cddb4a9444c55 Gerrit-Change-Number: 56174 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add missing devices to pci_devs.h
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56172 ) Change subject: soc/intel/alderlake: Add missing devices to pci_devs.h ...................................................................... soc/intel/alderlake: Add missing devices to pci_devs.h There were some devices missing from pci_devs.h: 1) GNA 2) I2C6 and I2C7 3) UART3, UART4, UART5, UART6 4) UFS 5) GSPI4, GSPI5, GSPI6 BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56172 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/include/soc/pci_devs.h 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 1e8ecc7..1729160 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -56,6 +56,10 @@ #define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) + #define SA_DEV_SLOT_TMT 0x0A #define SA_DEVFN_TMT _SA_DEVFN(TMT) #define SA_DEV_TMT _SA_DEV(TMT) @@ -79,20 +83,42 @@ /* PCH Devices */ #define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 #define PCH_DEV_SLOT_SIO0 0x10 +#define PCH_DEVFN_I2C6 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(SIO0, 1) #define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) #define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_I2C6 _PCH_DEV(SIO0, 0) +#define PCH_DEV_I2C7 _PCH_DEV(SIO0, 1) #define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) #define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) +#define PCH_DEV_SLOT_SIO6 0x11 +#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO6, 0) +#define PCH_DEVFN_UART4 _PCH_DEVFN(SIO6, 1) +#define PCH_DEVFN_UART5 _PCH_DEVFN(SIO6, 2) +#define PCH_DEVFN_UART6 _PCH_DEVFN(SIO6, 3) +#define PCH_DEV_UART3 _PCH_DEV(SIO6, 0) +#define PCH_DEV_UART4 _PCH_DEV(SIO6, 1) +#define PCH_DEV_UART5 _PCH_DEV(SIO6, 2) +#define PCH_DEV_UART6 _PCH_DEV(SIO6, 3) + #define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) #define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) +#define PCH_DEVFN_UFS _PCH_DEVFN(ISH, 7) #define PCH_DEV_ISH _PCH_DEV(ISH, 0) #define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) +#define PCH_DEV_UFS _PCH_DEV(ISH, 7) #define PCH_DEV_SLOT_SIO2 0x13 #define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_GSPI4 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_GSPI5 _PCH_DEVFN(SIO2, 2) +#define PCH_DEVFN_GSPI6 _PCH_DEVFN(SIO2, 3) #define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) +#define PCH_DEV_GSPI4 _PCH_DEV(SIO2, 1) +#define PCH_DEV_GSPI5 _PCH_DEV(SIO2, 2) +#define PCH_DEV_GSPI6 _PCH_DEV(SIO2, 3) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/56172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 Gerrit-Change-Number: 56172 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: remove unneeded line break
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56180 ) Change subject: soc/amd/picasso,stoneyridge/mca: remove unneeded line break ...................................................................... soc/amd/picasso,stoneyridge/mca: remove unneeded line break Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56180 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 2576f6e..12d4ccc 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -184,8 +184,7 @@ i, mci.cmask.hi, mci.cmask.lo); mci.bank = i; - if (CONFIG(ACPI_BERT) - && mca_valid(mci.sts)) + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } } diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index b1f955f..346cd6d 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -186,8 +186,7 @@ i, mci.cmask.hi, mci.cmask.lo); mci.bank = i; - if (CONFIG(ACPI_BERT) - && mca_valid(mci.sts)) + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/56180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Gerrit-Change-Number: 56180 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: enable psp_verstage by default
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55832 ) Change subject: mb/google/guybrush: enable psp_verstage by default ...................................................................... mb/google/guybrush: enable psp_verstage by default Select VBOOT_STARTS_BEFORE_BOOTBLOCK to turn on psp_verstage by default. BUG=b:182477057 TEST=boot guybrush Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55832 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 7c5aec6..f9c577a 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -48,7 +48,7 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_SEPARATE_VERSTAGE - select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_STARTS_BEFORE_BOOTBLOCK config VBOOT_STARTS_IN_BOOTBLOCK select NO_EARLY_BOOTBLOCK_POSTCODES -- To view, visit https://review.coreboot.org/c/coreboot/+/55832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08befb93213aeb67e6a1e5fa91273ae61025707e Gerrit-Change-Number: 55832 Gerrit-PatchSet: 2 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021