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Change subject: mb/google/poppy: Deduplicate lockdown config
......................................................................
mb/google/poppy: Deduplicate lockdown config
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.
Change-Id: I0bf3a6c91731d2ea8bc2f46c1276c7b66e63eb31
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
6 files changed, 0 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/56200/5
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Hello build bot (Jenkins), Tim Wawrzynczak, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56199
to look at the new patch set (#5).
Change subject: mb/google/volteer: Deduplicate lockdown config
......................................................................
mb/google/volteer: Deduplicate lockdown config
The setting `chipset_lockdown` has the same configuration for all
variants and they also match with the baseboard configuration. Thus,
remove it from the variant overridetrees.
Change-Id: I597e4487e7a0e1848d2a2f2c8f8ebd552994aac2
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/google/volteer/variants/chronicler/overridetree.cb
M src/mainboard/google/volteer/variants/collis/overridetree.cb
M src/mainboard/google/volteer/variants/copano/overridetree.cb
M src/mainboard/google/volteer/variants/delbin/overridetree.cb
M src/mainboard/google/volteer/variants/drobit/overridetree.cb
M src/mainboard/google/volteer/variants/eldrid/overridetree.cb
M src/mainboard/google/volteer/variants/elemi/overridetree.cb
M src/mainboard/google/volteer/variants/lindar/overridetree.cb
M src/mainboard/google/volteer/variants/volteer/overridetree.cb
M src/mainboard/google/volteer/variants/volteer2/overridetree.cb
10 files changed, 0 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56199/5
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56161 )
Change subject: soc/intel/common: Use SPR for backing up data way and eviction mask
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Hi Nick, Karthik,
If you could help to review for TGL and JSL. Thanks,
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56198
to look at the new patch set (#3).
Change subject: mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT
......................................................................
mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown.
Change-Id: Iee4f6986e5edfe1bf6c84fe132bcb47b15bb81f5
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/siemens/chili/variants/base/devicetree.cb
M src/mainboard/siemens/chili/variants/chili/devicetree.cb
2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/56198/3
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56179 )
Change subject: include/cpu/x86/msr: fix MCG_CTL_P definition
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56179/comment/90bbfcf6_8609116e
PS1, Line 10: that MSR contain the number of MCA banks being present on the CPU.
Please mention that the `MCG_CTL_P` macro is not used anywhere.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50053 )
Change subject: mb/{asrock,intel,siemens}: Define `.chipset_lockdown`
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/siemens/chili/variants/chili/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/50053/comment/a2688abf_4fdc4e90
PS6, Line 13: .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
> IIRC, we didn't set it on purpose. The coreboot path seemed unfinished […]
Turns out that the LOCKDOWN_FSP path is broken by now (we can't flash
internally anymore with it). I'll give up on upstream security for the
time being. As long as Intel is "contributing", it seems impossible.
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Change subject: mb/siemens/chili: Use CHIPSET_LOCKDOWN_COREBOOT
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56198/comment/e735c584_36414b25
PS2, Line 9: Let coreboot do chipset lockdown.
Mention the reason, e.g. "Internal flashing is not possible with FSP lockdown.".
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51374
to look at the new patch set (#11).
Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
......................................................................
soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used
to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates
the maximum numbers of bits that may be set in any of the SF MASK
register. Hence, this patch calculates SF way count to program SF
Mask#1 using below logic:
1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f
2. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - ((1 << data_ways) - 1)
Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/include/cpu/x86/msr.h
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
2 files changed, 11 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51374/11
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