coreboot-gerrit July 2021

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Change in coreboot[master]: mb/google/brya/variants/primus: Update GPIO for PS8811 init
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56157 ) Change subject: mb/google/brya/variants/primus: Update GPIO for PS8811 init ...................................................................... mb/google/brya/variants/primus: Update GPIO for PS8811 init Route GPP_D14 to USB_A1_RT_RST_ODL for PS8811 init sequence BUG=b:193099675 Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56157 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index a25ab29..21ffedf 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -35,8 +35,8 @@ PAD_NC(GPP_D6, NONE), /* D13 : ISH_UART0_RXD ==> NC */ PAD_NC(GPP_D13, NONE), - /* D14 : ISH_UART0_TXD ==> NC */ - PAD_NC(GPP_D14, NONE), + /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), /* E3 : PROC_GP0 ==> NC */ PAD_NC(GPP_E3, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/56157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia950da61a50f30f7c4aaef572c5ed162ee76dd0e Gerrit-Change-Number: 56157 Gerrit-PatchSet: 3 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Set max Pkg C-states to Auto
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55706 ) Change subject: soc/intel/alderlake: Set max Pkg C-states to Auto ...................................................................... soc/intel/alderlake: Set max Pkg C-states to Auto This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55706 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 709ab3c..077a58d 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -71,6 +71,24 @@ #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) +/* + * The Max Pkg Cstate + * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, + * 254 - CPU Default , 255 - Auto. + */ +enum pkgcstate_limit { + LIMIT_C0_C1 = 0, + LIMIT_C2 = 1, + LIMIT_C3 = 2, + LIMIT_C6 = 3, + LIMIT_C7 = 4, + LIMIT_C7S = 5, + LIMIT_C8 = 6, + LIMIT_C9 = 7, + LIMIT_C10 = 8, + LIMIT_CPUDEFAULT = 254, + LIMIT_AUTO = 255, +}; struct soc_intel_alderlake_config { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5b0d631..6faa393 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -533,6 +533,7 @@ s_cfg->PsOnEnable = 1; /* Enable the energy efficient turbo mode */ s_cfg->EnergyEfficientTurbo = 1; + s_cfg->PkgCStateLimit = LIMIT_AUTO; } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/55706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Gerrit-Change-Number: 55706 Gerrit-PatchSet: 9 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Update generic device number for mipi_camera device
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56162 ) Change subject: mb/google/brya: Update generic device number for mipi_camera device ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56162/comment/7072e1cb_ce302872 PS1, Line 9: overrites overrides https://review.coreboot.org/c/coreboot/+/56162/comment/a31f4704_d96185bf PS1, Line 9: device devices -- To view, visit https://review.coreboot.org/c/coreboot/+/56162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I034cb7da787313d1cb53484922149589ac0f1c5a Gerrit-Change-Number: 56162 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 04:26:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable EC software sync
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56154 ) Change subject: mb/intel/adlrvp_m: Enable EC software sync ...................................................................... mb/intel/adlrvp_m: Enable EC software sync This patch enables CONFIG_VBOOT_EARLY_EC_SYNC. EC software sync will be performed in romstage. BUG=None BRANCH=None TEST=Verify EC software sync works on adlrvp_m Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56154 Reviewed-by: Selma Bensaid <selma.bensaid(a)intel.com> Reviewed-by: Anil Kumar K <anil.kumar.k(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Selma Bensaid: Looks good to me, but someone else must approve Anil Kumar K: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 954c02e..8ed37ab 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -27,7 +27,6 @@ select GBB_FLAG_FORCE_MANUAL_RECOVERY select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE - select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC config MAINBOARD_DIR string @@ -96,6 +95,7 @@ select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC + select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC config UART_FOR_CONSOLE int -- To view, visit https://review.coreboot.org/c/coreboot/+/56154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a13094e5da2f672a6789fe86528de44e909045e Gerrit-Change-Number: 56154 Gerrit-PatchSet: 2 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) sil...
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Rizwan Qureshi, Sridhar Siricilla. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56073 ) Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) silicon ...................................................................... Patch Set 1: (3 comments) File src/mainboard/intel/adlrvp/bootblock.c: https://review.coreboot.org/c/coreboot/+/56073/comment/edd1b77f_efea1a52 PS1, Line 5: #include <console/console.h> We do sort our include in an alphabetical order. https://review.coreboot.org/c/coreboot/+/56073/comment/80f3f1d3_2857db19 PS1, Line 9: include <console/console.h> This include is already there on line 5. https://review.coreboot.org/c/coreboot/+/56073/comment/471d5145_4182efbe PS1, Line 36: if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { : printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); : return; : } : : if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) : != SI_DESC_REGION_SZ) { : printk(BIOS_ERR, "Failed to update Descriptor Region\n"); : return; : } Isn't this only possible if you have granted write permission to the x86 host for the descriptor region? Would it make sense to check this to avoid a endless reset-loop here if the write permission is missing? -- To view, visit https://review.coreboot.org/c/coreboot/+/56073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Gerrit-Change-Number: 56073 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 04:18:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/metaknight: Turn off lte power when s0ix
by David Wu (Code Review) 12 Jul '21

12 Jul '21

David Wu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55249 ) Change subject: mb/google/dedede/var/metaknight: Turn off lte power when s0ix ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78a39d8cd7a348ad36be9b5969f5c75ed48df833 Gerrit-Change-Number: 55249 Gerrit-PatchSet: 6 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brya: Create kano variant
by Werner Zeh (Code Review) 12 Jul '21

12 Jul '21

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56155 ) Change subject: mb/google/brya: Create kano variant ...................................................................... mb/google/brya: Create kano variant Create the kano variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:193052432 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_KANO Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56155 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/kano/include/variant/ec.h A src/mainboard/google/brya/variants/kano/include/variant/gpio.h A src/mainboard/google/brya/variants/kano/memory/Makefile.inc A src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/kano/overridetree.cb 8 files changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 814b782..58635e9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -78,6 +78,7 @@ default "Primus" if BOARD_GOOGLE_PRIMUS default "Gimble" if BOARD_GOOGLE_GIMBLE default "Redrix" if BOARD_GOOGLE_REDRIX + default "Kano" if BOARD_GOOGLE_KANO config VARIANT_DIR string @@ -85,6 +86,7 @@ default "primus" if BOARD_GOOGLE_PRIMUS default "gimble" if BOARD_GOOGLE_GIMBLE default "redrix" if BOARD_GOOGLE_REDRIX + default "kano" if BOARD_GOOGLE_KANO config DIMM_SPD_SIZE int diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 15e3bd0..4d1748e 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -24,3 +24,7 @@ config BOARD_GOOGLE_REDRIX bool "-> Redrix" select BOARD_GOOGLE_BASEBOARD_BRYA + +config BOARD_GOOGLE_KANO + bool "-> Kano" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/kano/include/variant/ec.h b/src/mainboard/google/brya/variants/kano/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/kano/include/variant/gpio.h b/src/mainboard/google/brya/variants/kano/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/kano/memory/Makefile.inc b/src/mainboard/google/brya/variants/kano/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt new file mode 100644 index 0000000..9cff262 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x. +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/56155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0670e346c113291054cb92fb57aae52f844e8c7 Gerrit-Change-Number: 56155 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8195: fine tune pmif spi hardware settings for stability
by Hung-Te Lin (Code Review) 12 Jul '21

12 Jul '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56166 ) Change subject: soc/mediatek/mt8195: fine tune pmif spi hardware settings for stability ...................................................................... soc/mediatek/mt8195: fine tune pmif spi hardware settings for stability Update IO driving setting for pmif spi. Signed-off-by: James Lo <james.lo(a)mediatek.corp-partner.google.com> Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/56166 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/include/soc/iocfg.h M src/soc/mediatek/mt8195/pmif_spi.c 2 files changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/include/soc/iocfg.h b/src/soc/mediatek/mt8195/include/soc/iocfg.h index 8ca2f62..f3524dc 100644 --- a/src/soc/mediatek/mt8195/include/soc/iocfg.h +++ b/src/soc/mediatek/mt8195/include/soc/iocfg.h @@ -63,5 +63,6 @@ enum { IO_4_MA = 0x9, + IO_6_MA = 0x1b, }; #endif /* __SOC_MEDIATEK_MT8195_IOCFG_H__ */ diff --git a/src/soc/mediatek/mt8195/pmif_spi.c b/src/soc/mediatek/mt8195/pmif_spi.c index ddb2175..eff4a21 100644 --- a/src/soc/mediatek/mt8195/pmif_spi.c +++ b/src/soc/mediatek/mt8195/pmif_spi.c @@ -10,7 +10,7 @@ void pmif_spi_iocfg(void) { - /* Set SoC SPI IO driving strength to 4 mA */ - SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_4_MA); - SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_4_MA); + /* Set SoC SPI IO driving strength to 6 mA */ + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg1, PWRAP_SPI0_DRIVING, IO_6_MA); + SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, PWRAP_SPI1_DRIVING, IO_6_MA); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48268cda8845a591592d8ca828ffe492e6dfe0ce Gerrit-Change-Number: 56166 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings
by Hung-Te Lin (Code Review) 12 Jul '21

12 Jul '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56106 ) Change subject: vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings ...................................................................... vc/mediatek/mt8195: Enable DRAM Vcore DVFS settings Add the implementation for vcore voltage control. Also remove the reporting of vio18 because it is fixed during DRAM init, and we won't provide drivers for reading or writing it. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56106 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c 2 files changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index b761473..b5de592 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -272,7 +272,6 @@ #ifndef DDR_INIT_TIME_PROFILING print("Read voltage for %d, %d\n", p->frequency, vGet_Current_SRAMIdx(p)); - print("Vio18 = %d\n", dramc_get_vio18_voltage()); print("Vcore = %d\n", dramc_get_vcore_voltage()); print("Vdram = %d\n", dramc_get_vmdd_voltage(p->dram_type)); print("Vddq = %d\n", dramc_get_vmddq_voltage(p->dram_type)); diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c index 570c976..5662412 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c @@ -352,8 +352,13 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_set_voltage(&reg_vcore, vcore, MAX_VCORE); -#endif +#elif defined(FOR_COREBOOT) + dramc_debug("%s set vcore to %u\n", __func__, vcore); + mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore); return 0; +#else + return 0; +#endif } unsigned int dramc_get_vcore_voltage(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/56106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39342aea902a87cdc2c5b862e5d1a889fcc822c5 Gerrit-Change-Number: 56106 Gerrit-PatchSet: 12 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/mediatek/mt8195: add FOR_COREBOOT define
by Hung-Te Lin (Code Review) 12 Jul '21

12 Jul '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56158 ) Change subject: vc/mediatek/mt8195: add FOR_COREBOOT define ...................................................................... vc/mediatek/mt8195: add FOR_COREBOOT define The CONFIG(CHROMEOS) in DRAM calibration code was incorrectly used to identify implementations for Chromebooks (in coreboot) so we want to introduce a new flag FOR_COREBOOT to prevent confusion. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de Reviewed-on: https://review.coreboot.org/c/coreboot/+/56158 Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/mediatek/mt8195/Makefile.inc M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c 2 files changed, 13 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/vendorcode/mediatek/mt8195/Makefile.inc b/src/vendorcode/mediatek/mt8195/Makefile.inc index 2dd5d09..0873ae3 100644 --- a/src/vendorcode/mediatek/mt8195/Makefile.inc +++ b/src/vendorcode/mediatek/mt8195/Makefile.inc @@ -3,3 +3,4 @@ CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8195/dramc/include -Isrc/vendorcode/mediatek/mt8195/include +CPPFLAGS_common += -DFOR_COREBOOT diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c index 1595073..570c976 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c @@ -360,7 +360,7 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(&reg_vcore); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VCORE); #else return 0; @@ -371,7 +371,7 @@ { #ifdef MTK_PMIC_MT6359 mtk_regulator_set_voltage(&reg_vdram, vdram, MAX_VDRAM); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VDD2, vdram); #endif return 0; @@ -381,7 +381,7 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(&reg_vdram); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VDD2); #else return 0; @@ -392,7 +392,7 @@ { #ifdef MTK_PMIC_MT6359 mtk_regulator_set_voltage(&reg_vddq, vddq, MAX_VDDQ); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VDDQ, vddq); #endif return 0; @@ -402,7 +402,7 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(&reg_vddq); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VDDQ); #else return 0; @@ -413,17 +413,19 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_set_voltage(&reg_vmddr, vmddr, MAX_VMDDR); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VMDDR, vmddr); -#endif return 0; +#else + return 0; +#endif } unsigned int dramc_get_vmddr_voltage(void) { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(&reg_vmddr); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VMDDR); #else return 0; @@ -434,7 +436,7 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_set_voltage(&reg_vio18, vio18, MAX_VIO18); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) mainboard_set_regulator_vol(MTK_REGULATOR_VDD1, vio18); return 0; #else @@ -447,7 +449,7 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_get_voltage(&reg_vio18); -#elif CONFIG(CHROMEOS) +#elif defined(FOR_COREBOOT) return mainboard_get_regulator_vol(MTK_REGULATOR_VDD1); #else return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/56158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a6e24f41c1fda167b5d6bb2d8a2c5c79dda8de Gerrit-Change-Number: 56158 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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