coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by Raul Rangel (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56228 ) Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality This change will make it so the standard rdev readat call will use the SPI DMA controller if the alignment is correct, and the transfer size is larger than 64 bytes. There is a magic bit that needs to be set for the SPI DMA controller to function correctly. This is only available in RN/CZN+. BUG=b:179699789 TEST=Boot guybrush to OS. This reduces loading verstage by 40ms, verifying RW by 500us and loading romstage by 500 us. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/spi_dma.c 2 files changed, 171 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56228/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 4e2660b..aa483e4 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -113,12 +113,24 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 +#define LPC_ROM_DMA_SRC_ADDR 0xb0 +#define LPC_ROM_DMA_DST_ADDR 0xb4 /* LPC register 0xb8 is DWORD, here there are definitions for byte access. For example, bits 31-24 are accessed through byte access at register 0xbb. */ -#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8 -#define SPI_FROM_HOST_PREFETCH_EN BIT(24) -#define SPI_FROM_USB_PREFETCH_EN BIT(23) +#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8 +#define SPI_FROM_HOST_PREFETCH_EN BIT(24) +#define SPI_FROM_USB_PREFETCH_EN BIT(23) +#define LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT 6 +#define LPC_ROM_DMA_CTRL_DW_COUNT_MASK (0x3ffUL << LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT) +#define LPC_ROM_DMA_CTRL_ERROR BIT(1) +#define LPC_ROM_DMA_CTRL_START BIT(0) +#define LPC_ROM_DMA_MIN_ALIGNMENT (1 << 6) +#define LPC_ROM_DMA_CTRL_DW_COUNT(bytes) \ + (((bytes / LPC_ROM_DMA_MIN_ALIGNMENT) - 1) << LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT) +#define LPC_ROM_DMA_CTRL_MAX_BYTES \ + (((LPC_ROM_DMA_CTRL_DW_COUNT_MASK >> LPC_ROM_DMA_CTRL_DW_COUNT_SHIFT) + 1) \ + * LPC_ROM_DMA_MIN_ALIGNMENT) #define LPC_HOST_CONTROL 0xbb #define PREFETCH_EN_SPI_FROM_HOST BIT(0) diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index 470bfb1..9bee259 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -1,8 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/lpc.h> +#include <amdblocks/spi.h> +#include <assert.h> #include <boot_device.h> -#include <commonlib/helpers.h> +#include <commonlib/bsd/cb_err.h> +#include <commonlib/bsd/helpers.h> #include <commonlib/region.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> #include <spi_flash.h> #include <string.h> #include <types.h> @@ -10,6 +18,14 @@ /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL - CONFIG_ROM_SIZE)) +struct spi_dma_transaction { + uint8_t *target; + size_t offset; + size_t size; + size_t transfer_size; + size_t remaining; +}; + static void *spi_dma_mmap(const struct region_device *rd, size_t offset, size_t size __unused) { const struct mem_region_device *mdev; @@ -36,10 +52,134 @@ return size; } +static bool spi_dma_is_busy(void) +{ + return pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL) + & LPC_ROM_DMA_CTRL_START; +} + +static bool spi_dma_has_error(void) +{ + return pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL) + & LPC_ROM_DMA_CTRL_ERROR; +} + +static bool can_use_dma(void *target, size_t offset, size_t size) +{ + if (!IS_ALIGNED((uintptr_t)target, LPC_ROM_DMA_MIN_ALIGNMENT)) + return false; + + if (!IS_ALIGNED(offset, LPC_ROM_DMA_MIN_ALIGNMENT)) + return false; + + return true; +} + +static void start_spi_dma_transaction(struct spi_dma_transaction *transaction) +{ + uint32_t ctrl; + + printk(BIOS_SPEW, "%s: dest: %p, offset: %#zx, remaining: %zu\n", __func__, + transaction->target, transaction->offset, transaction->remaining); + + /* + * We should have complete control over the DMA controller, so there shouldn't + * be any outstanding transactions. + */ + assert(!spi_dma_is_busy()); + assert(IS_ALIGNED((uintptr_t)transaction->target, LPC_ROM_DMA_MIN_ALIGNMENT)); + assert(IS_ALIGNED(transaction->offset, LPC_ROM_DMA_MIN_ALIGNMENT)); + assert(transaction->remaining >= LPC_ROM_DMA_MIN_ALIGNMENT); + + pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_SRC_ADDR, transaction->offset); + pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_DST_ADDR, (uintptr_t)transaction->target); + + ctrl = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); + ctrl &= ~LPC_ROM_DMA_CTRL_DW_COUNT_MASK; + + transaction->transfer_size = MIN(LPC_ROM_DMA_CTRL_MAX_BYTES, transaction->remaining); + + ctrl |= LPC_ROM_DMA_CTRL_DW_COUNT(transaction->transfer_size); + ctrl |= LPC_ROM_DMA_CTRL_ERROR; /* Clear error */ + ctrl |= LPC_ROM_DMA_CTRL_START; + + pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, ctrl); +} + +/* Returns true of transaction is still in progress. */ +static bool continue_spi_dma_transaction(const struct region_device *rd, + struct spi_dma_transaction *transaction) +{ + /* Verify we are looking at the correct transaction */ + assert(pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_SRC_ADDR) == transaction->offset); + + if (spi_dma_is_busy()) + return true; + + if (spi_dma_has_error()) + return false; + + transaction->target += transaction->transfer_size; + transaction->offset += transaction->transfer_size; + transaction->remaining -= transaction->transfer_size; + + if (transaction->remaining >= LPC_ROM_DMA_MIN_ALIGNMENT) { + start_spi_dma_transaction(transaction); + return true; + } else if (transaction->remaining > 0) { + /* Use mmap to finish off the transfer */ + spi_dma_readat_mmap(rd, transaction->target, transaction->offset, + transaction->remaining); + + transaction->target += transaction->remaining; + transaction->offset += transaction->remaining; + transaction->remaining -= transaction->remaining; + } + + return false; +} + +static ssize_t spi_dma_readat_dma(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + struct spi_dma_transaction transaction = { + .target = b, + .offset = offset, + .size = size, + .remaining = size, + }; + + printk(BIOS_SPEW, "%s: start: dest: %p, offset: %#zx, size: %zu\n", __func__, b, offset, + size); + + start_spi_dma_transaction(&transaction); + + do { + udelay(10); + } while (continue_spi_dma_transaction(rd, &transaction)); + + printk(BIOS_SPEW, "%s: end: dest: %p, offset: %#zx, size: %zu, remaining: %zu\n", + __func__, b, offset, size, transaction.remaining); + + return transaction.size - transaction.remaining; +} + +static ssize_t spi_dma_readat(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + assert(offset + size < CONFIG_ROM_SIZE); + assert(size); + + if (size < LPC_ROM_DMA_MIN_ALIGNMENT || !can_use_dma(b, offset, size)) + return spi_dma_readat_mmap(rd, b, offset, size); + else + return spi_dma_readat_dma(rd, b, offset, size); +} + const struct region_device_ops spi_dma_rdev_ro_ops = { .mmap = spi_dma_mmap, .munmap = spi_dma_munmap, - .readat = spi_dma_readat_mmap, + .readat = spi_dma_readat, }; static const struct mem_region_device boot_dev = { @@ -60,3 +200,17 @@ return 1; } + +/* Fix the SPI DMA controller */ +static void spi_dma_fix(void) +{ + /* Internal only registers */ + uint8_t val = spi_read8(0xfc); + val |= BIT(6); + spi_write8(0xfc, val); +} + +void boot_device_init(void) +{ + spi_dma_fix(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/cezanne: Move APOB update into ramstage
by Raul Rangel (Code Review) 12 Jul '21

12 Jul '21

1 0

Change in coreboot[master]: thread: Add missing static inline
by Raul Rangel (Code Review) 12 Jul '21

12 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56226 ) Change subject: thread: Add missing static inline ...................................................................... thread: Add missing static inline BUG=b:179699789 TEST=Able to compile Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3 --- M src/include/thread.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/56226/1 diff --git a/src/include/thread.h b/src/include/thread.h index a2c7ed2..da8ed72 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -59,6 +59,11 @@ #else static inline void threads_initialize(void) {} static inline int thread_run(void (*func)(void *), void *arg) { return -1; } +static inline int thread_run_until(void (*func)(void *), void *arg, boot_state_t state, + boot_state_sequence_t seq) +{ + return -1; +} static inline int thread_yield_microseconds(unsigned int microsecs) { return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/56226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3 Gerrit-Change-Number: 56226 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/common/block/apob: Fix incorrect printf format
by Raul Rangel (Code Review) 12 Jul '21

12 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56225 ) Change subject: soc/amd/common/block/apob: Fix incorrect printf format ...................................................................... soc/amd/common/block/apob: Fix incorrect printf format The %p format specifier already prints out 0x, so remove the 0x from the string. I also updated the other format specifiers to use the %# syntax to print out the 0x. BUG=b:179699789 TEST=see correct format. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec --- M src/soc/amd/common/block/apob/apob_cache.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/56225/1 diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index 238ae7a..34d5472 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -131,7 +131,7 @@ return; } - printk(BIOS_SPEW, "Copy APOB from RAM 0x%p/0x%x to flash 0x%zx/0x%zx\n", + printk(BIOS_SPEW, "Copy APOB from RAM %p/%#x to flash %#zx/%#zx\n", apob_src_ram, apob_src_ram->size, region_offset(&region), region_sz(&region)); -- To view, visit https://review.coreboot.org/c/coreboot/+/56225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec Gerrit-Change-Number: 56225 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: [DO NOT SUBMIT] util/kconfig: Get more information on failure
by Patrick Georgi (Code Review) 12 Jul '21

12 Jul '21

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56224 ) Change subject: [DO NOT SUBMIT] util/kconfig: Get more information on failure ...................................................................... Abandoned not needed anymore -- To view, visit https://review.coreboot.org/c/coreboot/+/56224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26a32836fea7cf42d3c0ca3f9398e566d69690da Gerrit-Change-Number: 56224 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: trogdor: sc7180: Rename header files as per common QUP driver changes
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55959 ) Change subject: trogdor: sc7180: Rename header files as per common QUP driver changes ...................................................................... Patch Set 5: (3 comments) Patchset: PS5: This CL seems like it should be split among the various sc7180 refactors previously in the CL stack. Please split it out accordingly so we don't get into a state where sc7180 is in a broken state. File src/mainboard/google/trogdor/bootblock.c: https://review.coreboot.org/c/coreboot/+/55959/comment/0569df8f_664c15f6 PS5, Line 5: #include <soc/qupv3_spi_common.h> Shouldn't this be included in the sc7180 spi driver refactor? Otherwise it won't compile at this point... File src/mainboard/google/trogdor/mainboard.c: https://review.coreboot.org/c/coreboot/+/55959/comment/05456ada_11e6e94a PS5, Line 12: #include <soc/qupv3_config_common.h> Seems like these should be included in their respective sc7180 driver refactors. Otherwise sc7180 will be at a point where it won't compile anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/55959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a4f28b77e3942a4c6069b1785b0c6ac5b7e0a2 Gerrit-Change-Number: 55959 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 21:49:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/intel/txt: use mca_get_bank_count()
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56187 ) Change subject: security/intel/txt: use mca_get_bank_count() ...................................................................... security/intel/txt: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Change-Id: I28244c975ee34d36d0b44df092d4a62a01c3c79c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56187 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/security/intel/txt/common.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 239e152..011e8cc 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -481,8 +481,7 @@ * Make sure there are no uncorrectable MCE errors. * Intel 64 and IA-32 Architectures Software Developer Manuals Vol 2D */ - msr = rdmsr(IA32_MCG_CAP); - size_t max_mc_msr = msr.lo & MCA_BANKS_MASK; + size_t max_mc_msr = mca_get_bank_count(); for (size_t i = 0; i < max_mc_msr; i++) { msr = rdmsr(IA32_MC0_STATUS + 4 * i); if (!(msr.hi & MCA_STATUS_HI_UC)) -- To view, visit https://review.coreboot.org/c/coreboot/+/56187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28244c975ee34d36d0b44df092d4a62a01c3c79c Gerrit-Change-Number: 56187 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/qualcomm/common/uart: Add support for UART common driver
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55954 ) Change subject: soc/qualcomm/common/uart: Add support for UART common driver ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Can you put in the commit message that these files were copied over from soc/qualcomm/sc7180 so people know that you are just moving code as opposed to creating brand new code? -- To view, visit https://review.coreboot.org/c/coreboot/+/55954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc2d3765f956e04bae3e45c3a9b9e2ad424c7b1 Gerrit-Change-Number: 55954 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 21:37:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7180: Refactor SPI driver
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55957 ) Change subject: sc7180: Refactor SPI driver ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Can you put in the commit message that these files were copied over from soc/qualcomm/sc7180 so people know that you are just moving code as opposed to creating brand new code? -- To view, visit https://review.coreboot.org/c/coreboot/+/55957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c57f8650271287a1b3ccce9bd62fce6987d785e Gerrit-Change-Number: 55957 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 21:35:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/kblrvp: Rework Kconfig
by Felix Singer (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Felix Singer. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56219 ) Change subject: mb/intel/kblrvp: Rework Kconfig ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/56219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a Gerrit-Change-Number: 56219 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Mon, 12 Jul 2021 21:34:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021