coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: Enable bootblock compression
by Shelley Chen (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Ravi kumar, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52131 ) Change subject: sc7280: Enable bootblock compression ...................................................................... Patch Set 28: (1 comment) File src/soc/qualcomm/sc7280/Kconfig: https://review.coreboot.org/c/coreboot/+/52131/comment/be63f494_c07d89bb PS14, Line 16: select HAVE_UART_SPECIAL : select BOOTBLOCK_CONSOLE these don't seem to be related to the compression of the bootblock. Are they necessary for this CL or were they just left out before? If they're unrelated, I'd prefer if they were either explicitly called out in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/52131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3564a7e531d769c8df16a1592ea98133d83b07b0 Gerrit-Change-Number: 52131 Gerrit-PatchSet: 28 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 22:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Move APOB update into ramstage
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56227 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Move APOB update into ramstage ...................................................................... soc/amd/cezanne: Move APOB update into ramstage There is no technical reason this needs to be done in romstage. Moving it into ramstage allow us to use threads to pre-load the apob from SPI. BUG=b:179699789 TEST=Boot and picasso cezanne and verify APOB update still work Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e --- M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/apob/Makefile.inc M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/include/amdblocks/apob_cache.h M src/soc/amd/picasso/romstage.c 5 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/56227/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Gerrit-Change-Number: 56227 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: herobrine: sc7280: Load GSI FW in ramstage
by Shelley Chen (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Ravi kumar, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55964 ) Change subject: herobrine: sc7280: Load GSI FW in ramstage ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/herobrine/bootblock.c: https://review.coreboot.org/c/coreboot/+/55964/comment/538210f1_72299fe3 PS5, Line 5: #include <soc/qcom_qup_se.h> : #include <soc/qup_se_handlers_common.h> : #include <soc/qupv3_spi_common.h> > We don't need these until we use them in bootblock right? Please move these includes to: https://review.coreboot.org/c/coreboot/+/50581/ -- To view, visit https://review.coreboot.org/c/coreboot/+/55964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Gerrit-Change-Number: 55964 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 22:01:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: sc7280: Load GSI FW in ramstage
by Shelley Chen (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Ravi kumar, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55964 ) Change subject: herobrine: sc7280: Load GSI FW in ramstage ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/herobrine/bootblock.c: https://review.coreboot.org/c/coreboot/+/55964/comment/d2c61488_f886cc19 PS5, Line 5: #include <soc/qcom_qup_se.h> : #include <soc/qup_se_handlers_common.h> : #include <soc/qupv3_spi_common.h> We don't need these until we use them in bootblock right? File src/mainboard/google/herobrine/mainboard.c: https://review.coreboot.org/c/coreboot/+/55964/comment/abbea9ab_4865fbf4 PS5, Line 21: > trailing whitespace Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/55964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Gerrit-Change-Number: 55964 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 21:59:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Start loading APOB asynchronously
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

1 0

Change in coreboot[master]: WIP: soc/amd/common/block/lpc: Don't disable the HOG bit
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

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Change in coreboot[master]: soc/amd/common/apob: Add support for asynchronously reading APOB
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56232 ) Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB ...................................................................... soc/amd/common/apob: Add support for asynchronously reading APOB This CL adds a method that can starts the processes of reading the APOB from SPI. It does require more RAM in ramstage since we no longer mmap the buffer in the async happy path. This will allow us to reduce our boot time by 10ms. BUG=b:179699789 TEST=With this and the patches above I can see a 10 ms reduction in boot time on guybrush. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 --- M src/soc/amd/common/block/apob/apob_cache.c 1 file changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56232/1 diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index c41627b..ecb7ea5 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -7,10 +7,13 @@ #include <bootstate.h> #include <commonlib/region.h> #include <console/console.h> +#include <delay.h> #include <fmap.h> #include <spi_flash.h> #include <stdint.h> #include <string.h> +#include <thread.h> +#include <timer.h> #include <timestamp.h> #define DEFAULT_MRC_CACHE "RW_MRC_CACHE" @@ -72,11 +75,65 @@ return 0; } +struct apob_thread_context { + uint8_t buffer[DEFAULT_MRC_CACHE_SIZE] __attribute__((aligned(64))); + struct thread_handle handle; + struct region_device apob_rdev; +} global_apob_thread; + +static enum cb_err apob_thread_entry(void *arg) +{ + ssize_t size; + struct apob_thread_context *thread = arg; + + printk(BIOS_ERR, "APOB thread running\n"); + size = rdev_readat(&thread->apob_rdev, thread->buffer, 0, + region_device_sz(&thread->apob_rdev)); + + if (size == region_device_sz(&thread->apob_rdev)) + return CB_SUCCESS; + + return CB_ERR; +} + +static void start_apob_cache_read(void *arg) +{ + struct region region; + struct apob_thread_context *thread = arg; + + /* We don't perform any comparison on S3 resume */ + if (acpi_is_wakeup_s3()) + return; + + if (get_nv_region(&region) != 0) + return; + + if (boot_device_ro_subregion(&region, &thread->apob_rdev) < 0) { + printk(BIOS_ERR, "Failed boot_device_ro_subregion\n"); + return; + } + + assert(ARRAY_SIZE(thread->buffer) == region_device_sz(&thread->apob_rdev)); + + printk(BIOS_INFO, "Starting APOB preload\n"); + if (thread_run_until(&thread->handle, apob_thread_entry, thread, BS_PAYLOAD_LOAD, + BS_ON_ENTRY)) + printk(BIOS_ERR, "Failed to start APOB preload thread\n"); +} + static void *get_apob_from_nv_region(struct region *region) { struct region_device read_rdev; struct apob_base_header apob_header; + if (wait_for_thread(&global_apob_thread.handle) == CB_SUCCESS) { + if (apob_header_valid((struct apob_base_header *)&global_apob_thread.buffer, + "ROM (Cached)")) + return global_apob_thread.buffer; + else + return NULL; + } + if (boot_device_ro_subregion(region, &read_rdev) < 0) { printk(BIOS_ERR, "Failed boot_device_ro_subregion\n"); return NULL; @@ -184,4 +241,9 @@ */ return get_apob_nv_address(); } + +#if CONFIG(COOP_MULTITASKING) +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_apob_cache_read, &global_apob_thread); +#endif + BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/56232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 Gerrit-Change-Number: 56232 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

1 0

Change in coreboot[master]: thread: Add mutex
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56230 ) Change subject: thread: Add mutex ...................................................................... thread: Add mutex We need a way to protect shared resources. Since we are using cooperative multitasking the mutex implementation is pretty trivial. BUG=b:179699789 TEST=Verify thread locks and unlocks Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff --- M src/include/thread.h M src/lib/thread.c 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/56230/1 diff --git a/src/include/thread.h b/src/include/thread.h index 902a7f7..9c68072 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -19,6 +19,10 @@ enum cb_err error; }; +struct mutex { + bool locked; +}; + #if ENV_RAMSTAGE && CONFIG(COOP_MULTITASKING) struct thread { @@ -63,6 +67,9 @@ /* Wait's until the thread has terminated and returns the error code */ enum cb_err wait_for_thread(struct thread_handle *handle); +void mutex_lock(struct mutex *mutex); +void mutex_unlock(struct mutex *mutex); + static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { ci->thread = NULL; @@ -101,6 +108,10 @@ struct cpu_info; static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } + +static inline void mutex_lock(struct mutex *mutex) {} + +static inline void mutex_unlock(struct mutex *mutex) {} #endif #endif /* THREAD_H_ */ diff --git a/src/lib/thread.c b/src/lib/thread.c index 671cb3e..f9a3fc6 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <stddef.h> #include <stdint.h> #include <stdlib.h> @@ -394,3 +395,22 @@ return handle->error; } + +void mutex_lock(struct mutex *mutex) +{ + struct stopwatch sw; + + stopwatch_init(&sw); + + while (mutex->locked) + thread_yield_microseconds(10); + mutex->locked = 1; + + printk(BIOS_DEBUG, " took %lu us to acquire mutex\n", stopwatch_duration_usecs(&sw)); +} + +void mutex_unlock(struct mutex *mutex) +{ + assert(mutex->locked); + mutex->locked = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff Gerrit-Change-Number: 56230 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: thread: Add thread_handle
by Raul Rangel (Code Review) 13 Jul '21

13 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56229 ) Change subject: thread: Add thread_handle ...................................................................... thread: Add thread_handle The thread_handle can be used to wait for a thread to exit. I also added a return value to the thread function that will be stored on the handle after it completes. This makes it easy for the callers to check if the thread completed successfully or had an error. The wait_for_thread method uses the handle to block until the thread completes. BUG=b:179699789 TEST=See thread_handle state update and see error code set correctly. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff --- M src/include/thread.h M src/lib/thread.c 2 files changed, 87 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/56229/1 diff --git a/src/include/thread.h b/src/include/thread.h index da8ed72..902a7f7 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -2,9 +2,22 @@ #ifndef THREAD_H_ #define THREAD_H_ -#include <stdint.h> -#include <bootstate.h> #include <arch/cpu.h> +#include <bootstate.h> +#include <commonlib/bsd/cb_err.h> +#include <stdint.h> + +enum thread_state { + THREAD_UNINITIALIZED, + THREAD_STARTED, + THREAD_DONE, +}; + +struct thread_handle { + enum thread_state state; + /* Only valid when state == THREAD_DONE */ + enum cb_err error; +}; #if ENV_RAMSTAGE && CONFIG(COOP_MULTITASKING) @@ -13,9 +26,10 @@ uintptr_t stack_current; uintptr_t stack_orig; struct thread *next; - void (*entry)(void *); + enum cb_err (*entry)(void *); void *entry_arg; int can_yield; + struct thread_handle *handle; }; void threads_initialize(void); @@ -26,12 +40,14 @@ void *arch_get_thread_stackbase(void); /* Run func(arrg) on a new thread. Return 0 on successful start of thread, < 0 * when thread could not be started. Note that the thread will block the - * current state in the boot state machine until it is complete. */ -int thread_run(void (*func)(void *), void *arg); + * current state in the boot state machine until it is complete. The thread + * handle if populated, will reflect the state and return code of the thread. + */ +int thread_run(struct thread_handle *handle, enum cb_err (*func)(void *), void *arg); /* thread_run_until is the same as thread_run() except that it blocks state * transitions from occurring in the (state, seq) pair of the boot state * machine. */ -int thread_run_until(void (*func)(void *), void *arg, +int thread_run_until(struct thread_handle *handle, enum cb_err (*func)(void *), void *arg, boot_state_t state, boot_state_sequence_t seq); /* Return 0 on successful yield for the given amount of time, < 0 when thread * did not yield. */ @@ -44,6 +60,9 @@ void thread_cooperate(void); void thread_prevent_coop(void); +/* Wait's until the thread has terminated and returns the error code */ +enum cb_err wait_for_thread(struct thread_handle *handle); + static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { ci->thread = NULL; @@ -58,9 +77,13 @@ asmlinkage void (*thread_entry)(void *), void *arg); #else static inline void threads_initialize(void) {} -static inline int thread_run(void (*func)(void *), void *arg) { return -1; } -static inline int thread_run_until(void (*func)(void *), void *arg, boot_state_t state, - boot_state_sequence_t seq) +static inline int thread_run(struct thread_handle *handle, enum cb_err (*func)(void *), + void *arg) +{ + return -1; +} +static inline int thread_run_until(struct thread_handle *handle, enum cb_err (*func)(void *), + void *arg, boot_state_t state, boot_state_sequence_t seq) { return -1; } @@ -70,6 +93,12 @@ } static inline void thread_cooperate(void) {} static inline void thread_prevent_coop(void) {} + +static inline enum cb_err wait_for_thread(struct thread_handle *handle) +{ + return CB_ERR; +} + struct cpu_info; static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } #endif diff --git a/src/lib/thread.c b/src/lib/thread.c index e2280c6..671cb3e 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -127,11 +127,20 @@ /* current is still runnable. */ push_runnable(current); } + + if (t->handle) + t->handle->state = THREAD_STARTED; + switch_to_thread(t->stack_current, &current->stack_current); } -static void terminate_thread(struct thread *t) +static void terminate_thread(struct thread *t, enum cb_err error) { + if (t->handle) { + t->handle->error = error; + t->handle->state = THREAD_DONE; + } + free_thread(t); schedule(NULL); } @@ -139,20 +148,23 @@ static void asmlinkage call_wrapper(void *unused) { struct thread *current = current_thread(); + enum cb_err error; - current->entry(current->entry_arg); - terminate_thread(current); + error = current->entry(current->entry_arg); + + terminate_thread(current, error); } /* Block the current state transitions until thread is complete. */ static void asmlinkage call_wrapper_block_current(void *unused) { struct thread *current = current_thread(); + enum cb_err error; boot_state_current_block(); - current->entry(current->entry_arg); + error = current->entry(current->entry_arg); boot_state_current_unblock(); - terminate_thread(current); + terminate_thread(current, error); } struct block_boot_state { @@ -165,18 +177,18 @@ { struct block_boot_state *bbs = arg; struct thread *current = current_thread(); + enum cb_err error; boot_state_block(bbs->state, bbs->seq); - current->entry(current->entry_arg); + error = current->entry(current->entry_arg); boot_state_unblock(bbs->state, bbs->seq); - terminate_thread(current); + terminate_thread(current, error); } /* Prepare a thread so that it starts by executing thread_entry(thread_arg). * Within thread_entry() it will call func(arg). */ -static void prepare_thread(struct thread *t, void *func, void *arg, - asmlinkage void (*thread_entry)(void *), - void *thread_arg) +static void prepare_thread(struct thread *t, struct thread_handle *handle, void *func, + void *arg, asmlinkage void (*thread_entry)(void *), void *thread_arg) { /* Stash the function and argument to run. */ t->entry = func; @@ -185,6 +197,9 @@ /* All new threads can yield by default. */ t->can_yield = 1; + /* Pointer used to publish the state of thread */ + t->handle = handle; + arch_prepare_thread(t, thread_entry, thread_arg); } @@ -206,7 +221,7 @@ die("No threads available for idle thread!\n"); /* Queue idle thread to run once all other threads have yielded. */ - prepare_thread(t, idle_thread, NULL, call_wrapper, NULL); + prepare_thread(t, NULL, idle_thread, NULL, call_wrapper, NULL); push_runnable(t); /* Mark the currently executing thread to cooperate. */ thread_cooperate(); @@ -268,7 +283,7 @@ idle_thread_init(); } -int thread_run(void (*func)(void *), void *arg) +int thread_run(struct thread_handle *handle, enum cb_err (*func)(void *), void *arg) { struct thread *current; struct thread *t; @@ -288,13 +303,13 @@ return -1; } - prepare_thread(t, func, arg, call_wrapper_block_current, NULL); + prepare_thread(t, handle, func, arg, call_wrapper_block_current, NULL); schedule(t); return 0; } -int thread_run_until(void (*func)(void *), void *arg, +int thread_run_until(struct thread_handle *handle, enum cb_err (*func)(void *), void *arg, boot_state_t state, boot_state_sequence_t seq) { struct thread *current; @@ -319,7 +334,7 @@ bbs = thread_alloc_space(t, sizeof(*bbs)); bbs->state = state; bbs->seq = seq; - prepare_thread(t, func, arg, call_wrapper_block_state, bbs); + prepare_thread(t, handle, func, arg, call_wrapper_block_state, bbs); schedule(t); return 0; @@ -360,3 +375,22 @@ if (current != NULL) current->can_yield = 0; } + +enum cb_err wait_for_thread(struct thread_handle *handle) +{ + struct stopwatch sw; + + if (handle->state == THREAD_UNINITIALIZED) + return CB_ERR_ARG; + + stopwatch_init(&sw); + + printk(BIOS_DEBUG, "waiting for thread\n"); + + while (handle->state != THREAD_DONE) + thread_yield_microseconds(10); + + printk(BIOS_DEBUG, " took %lu us\n", stopwatch_duration_usecs(&sw)); + + return handle->error; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Gerrit-Change-Number: 56229 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021