coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/intel/gma: Restructure Opregion version info code
by Furquan Shaikh (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Angel Pons, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56168 ) Change subject: drivers/intel/gma: Restructure Opregion version info code ...................................................................... Patch Set 8: Code-Review+2 (2 comments) File src/drivers/intel/gma/opregion.h: https://review.coreboot.org/c/coreboot/+/56168/comment/9352f4d8_84075928 PS8, Line 19: space not needed. https://review.coreboot.org/c/coreboot/+/56168/comment/162b83b6_b6e7cda0 PS8, Line 25: Align with rest of the entries for consistency. -- To view, visit https://review.coreboot.org/c/coreboot/+/56168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Gerrit-Change-Number: 56168 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:45:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Furquan Shaikh (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Martin Roth, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/460aad26_3240056c PS2, Line 13: however, some FSP 2.0 variants have it as well. Thanks for the pointers Nick. > The other option is to override this header file during FSP build but per discussion with Martin it seems to be a less desirable approach. Why is it less desirable approach? +Nate, +Subrata - do you know why FSP Header spec version wasn't updated as part of https://github.com/tianocore/edk2/commit/f2cdb268ef04eeec51948b5d81eeca5cab… Is the intention here that the PcdFspHeaderSpecVersion be overriden by the FSP package? I see that is what TGL is doing for example in `TigerLakeFspPkg.dsc` -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:32:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers
by Eric Peers (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56231 ) Change subject: soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56231/comment/ca1272eb_ded2bd0a PS2, Line 10: have multiple threads trhing to access the DMA hardware. nit: trying -- To view, visit https://review.coreboot.org/c/coreboot/+/56231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09 Gerrit-Change-Number: 56231 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:27:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: thread: Add mutex
by Eric Peers (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Raul Rangel, Julius Werner, Felix Held. Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56230 ) Change subject: thread: Add mutex ...................................................................... Patch Set 2: (1 comment) File src/lib/thread.c: https://review.coreboot.org/c/coreboot/+/56230/comment/2a53c274_ee1946a2 PS2, Line 406: thread_yield_microseconds(10); do we need an eventual timeout here to catch improper unlocks? -- To view, visit https://review.coreboot.org/c/coreboot/+/56230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff Gerrit-Change-Number: 56230 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:26:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: thread: Add thread_handle
by Eric Peers (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Raul Rangel, Julius Werner, Felix Held. Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56229 ) Change subject: thread: Add thread_handle ...................................................................... Patch Set 2: (1 comment) File src/include/thread.h: https://review.coreboot.org/c/coreboot/+/56229/comment/e0e66fa4_b5ca5d7c PS2, Line 63: /* Wait's until the thread has terminated and returns the error code */ nit: waits -- To view, visit https://review.coreboot.org/c/coreboot/+/56229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Gerrit-Change-Number: 56229 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:24:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
by Eric Peers (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56228 ) Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality ...................................................................... Patch Set 2: (3 comments) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/56228/comment/b62dc5b3_3b74e308 PS2, Line 69: if (!IS_ALIGNED((uintptr_t)target, LPC_ROM_DMA_MIN_ALIGNMENT)) given your comments about architectural constraints (RN, CZN+), do we need a check for that as well? https://review.coreboot.org/c/coreboot/+/56228/comment/95931424_b6c56a3d PS2, Line 119: if (spi_dma_has_error()) does this need to move above the busy check? https://review.coreboot.org/c/coreboot/+/56228/comment/b5a7ca4a_9cb8726c PS2, Line 158: udelay(10); why 10? will different spi speeds yield a different number here? -- To view, visit https://review.coreboot.org/c/coreboot/+/56228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Gerrit-Change-Number: 56228 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:22:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Move APOB update into ramstage
by Eric Peers (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56227 ) Change subject: soc/amd/cezanne: Move APOB update into ramstage ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56227/comment/db23610a_8c0afd3b PS2, Line 10: it into ramstage allow us to use threads to pre-load the apob from SPI. > Does it offer boot time savings? If so, can you please capture in the commit message regarding how m […] I thought we were storing the APOB to SPI in coreboot, where PSP is loading the APOB from SPI. Did I miss something? Are you really intending to optimize the compare instead? And could we simplify that whole piece by just hashing it instead? /* Save APOB buffer to flash */ void soc_update_apob_cache(void) https://review.coreboot.org/c/coreboot/+/56227/comment/6a5d35c9_ca066a9a PS2, Line 13: and picasso > Nit: Zork and Guybrush? Nit the Nit: Trembyle (or equiv) and Guybrush. -- To view, visit https://review.coreboot.org/c/coreboot/+/56227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Gerrit-Change-Number: 56227 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:18:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cbtable: Store loglevel with consoles
by Julius Werner (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55397 ) Change subject: cbtable: Store loglevel with consoles ...................................................................... Patch Set 7: (1 comment) File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/55397/comment/3f13bc34_4e44d0be PS7, Line 120: console->loglevel = get_console_loglevel(); I think this is the wrong tag, or at least this alone won't help our Chrome OS case. For some reason there are two "console" tags in the coreboot table, this one (which seems to only be used for USB EHCI console?), and lb_serial which is what depthcharge and Arm TF use to determine serial out. It would probably be best to combine those two somehow (e.g. lb_serial also has a `type` field which could be used to implement the functionality from here, and then the serial-specific fields could just be blank for non-serial consoles or something), if anyone even uses this one at all anymore. It's not even parsed by libpayload, so it would have to be one of those custom payloads. -- To view, visit https://review.coreboot.org/c/coreboot/+/55397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic32603ffac8ec9955aefa3d608dd324da9271811 Gerrit-Change-Number: 55397 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:06:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow configuring log level through CBFS
by Julius Werner (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Marc Jones, Nico Huber, Stefan Reinauer, Patrick Rudolph. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow configuring log level through CBFS ...................................................................... Patch Set 17: Code-Review+2 (3 comments) Patchset: PS17: Sorry for missing the June replies, they must have somehow slipped through my queue. I think this looks pretty good now. File src/console/Kconfig: https://review.coreboot.org/c/coreboot/+/45208/comment/f86fa98c_b343964a PS14, Line 43: config OPTIONAL_SLOW_CONSOLE > I dislike options so now that we cut down on the code, I made it a default behavior. Hmm... well, the cost for that extra lookup should be really trivial, so I guess as long as nobody complains it should be fine to have it on unconditionally. File tests/console/Makefile.inc: https://review.coreboot.org/c/coreboot/+/45208/comment/89da114a_beea8615 PS14, Line 10: routing-with-cbmemcons-test-cflags += -I 3rdparty/vboot/firmware/include > because we now draw in cbfs, and through that, vboot, and the unit testing framework minimizes API e […] I still don't really understand this. I think the include path for unit test builds should be the same as the one for normal coreboot builds (plus extra test-only header directories). If vboot is in the default include path for coreboot itself, I think we should also put it in the path for unit tests rather than requiring all tests that touch any file including vboot stuff to add custom cflags like this. -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 23:00:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: console: Handle verstage as "first non-bootblock stage"
by Julius Werner (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Nico Huber. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56210 ) Change subject: console: Handle verstage as "first non-bootblock stage" ...................................................................... Patch Set 1: (1 comment) File src/console/init.c: https://review.coreboot.org/c/coreboot/+/56210/comment/9fff15d7_f2ba5b2b PS1, Line 15: #endif I believe the NO_BOOTBLOCK_CONSOLE part here already made no sense to begin with, and this would be a good time to correct it. The reason we want to skip stuff in the "FIRST_CONSOLE" is because we're not sure if everything required will be initialized yet so early in the very first stage. But those dependencies aren't really console related, so when there is no bootblock console it doesn't make sense to transfer the same concerns to the next stage -- e.g. even when NO_BOOTBLOCK_CONSOLE is enabled, the bootblock will still set up CBFS (and whatever it may do for the option stuff), and we can still rely on that having been done in the next stage. (I hope Nico can chime in if he had something in mind with that code that I'm missing here.) On the other hand, you do need to take the VBOOT_BEFORE_BOOTBLOCK case into account, where verstage is actually the first stage and then the bootblock comes after that (I know, it's a mess... I asked them not to do it that way, but here we are :/ ). We already have ENV_INITIAL_STAGE that is used by CBFS and FMAP code to figure this out, I think that would be idea to be used here as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/56210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I494a33483e306a049aa0c8137a118644fc28177e Gerrit-Change-Number: 56210 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 22:58:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2021