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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: factor out mca_clear_errors
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: factor out mca_print_error()
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56239 ) Change subject: soc/amd/picasso,stoneyridge/mca: factor out mca_print_error() ...................................................................... soc/amd/picasso,stoneyridge/mca: factor out mca_print_error() Change-Id: I7cd05a389c34c2e5f3d0ab4cd06d60a7e3e5cad9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 42 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56239/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 07e700e..e525d03 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -145,6 +145,25 @@ "L3 cache unit" }; +static void mca_print_error(unsigned int bank) +{ + msr_t msr; + + printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, + bank < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[bank] : ""); + + msr = rdmsr(MCAX_STATUS_MSR(bank)); + printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCAX_ADDR_MSR(bank)); + printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCAX_MISC0_MSR(bank)); + printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCAX_CTL_MSR(bank)); + printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCA_CTL_MASK_MSR(bank)); + printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); +} + /* Check the Machine Check Architecture Extension registers */ void check_mca(void) { @@ -154,28 +173,11 @@ const unsigned int num_banks = mca_get_bank_count(); for (i = 0 ; i < num_banks ; i++) { + mci.bank = i; mci.sts = rdmsr(MCAX_STATUS_MSR(i)); if (mci.sts.hi || mci.sts.lo) { - printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", - initial_lapicid(), i, - i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : ""); + mca_print_error(i); - printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", - i, mci.sts.hi, mci.sts.lo); - msr = rdmsr(MCAX_ADDR_MSR(i)); - printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MCAX_MISC0_MSR(i)); - printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MCAX_CTL_MSR(i)); - printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MCA_CTL_MASK_MSR(i)); - printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", - i, msr.hi, msr.lo); - - mci.bank = i; if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 9425089..06b35bb 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -145,6 +145,25 @@ "Floating point unit" }; +static void mca_print_error(unsigned int bank) +{ + msr_t msr; + + printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, + mca_bank_name[bank]); + + msr = rdmsr(IA32_MC0_STATUS + (bank * 4)); + printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_ADDR + (bank * 4)); + printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_MISC + (bank * 4)); + printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_CTL + (bank * 4)); + printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MC0_CTL_MASK + bank); + printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); +} + void check_mca(void) { unsigned int i; @@ -157,27 +176,11 @@ if (i == 3) /* Reserved in Family 15h */ continue; + mci.bank = i; mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { - printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", - initial_lapicid(), i, mca_bank_name[i]); + mca_print_error(i); - printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", - i, mci.sts.hi, mci.sts.lo); - msr = rdmsr(IA32_MC0_ADDR + (i * 4)); - printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_MISC + (i * 4)); - printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_CTL + (i * 4)); - printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", - i, msr.hi, msr.lo); - msr = rdmsr(MC0_CTL_MASK + i); - printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", - i, msr.hi, msr.lo); - - mci.bank = i; if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) build_bert_mca_error(&mci); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cd05a389c34c2e5f3d0ab4cd06d60a7e3e5cad9 Gerrit-Change-Number: 56239 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: use unsigned int for MCA bank number
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

1 0

Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: clean up mca_bank struct
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56237 ) Change subject: soc/amd/picasso,stoneyridge/mca: clean up mca_bank struct ...................................................................... soc/amd/picasso,stoneyridge/mca: clean up mca_bank struct Only the fields bank and sts from the mca_bank struct were used outside a local scope, so remove the rest. Also rename the struct that now only contains the bank number and the status MSR content to mca_bank_status. Change-Id: I925347dff950ac2bd021635ca988c02fba48df7f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 34 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/56237/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 3c5dd10..84f3ead 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -13,13 +13,9 @@ /* MISC4 is the last used register in the MCAX banks of Picasso */ #define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) -struct mca_bank { +struct mca_bank_status { int bank; - msr_t ctl; msr_t sts; - msr_t addr; - msr_t misc; - msr_t cmask; }; static inline size_t mca_report_size_reqd(void) @@ -50,7 +46,7 @@ return size; } -static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci) +static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) { int error = mca_err_type(mci->sts); @@ -68,7 +64,7 @@ /* Fill additional information in the Generic Processor Error Section. */ static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank *mci) + struct mca_bank_status *mci) { int type = mca_err_type(mci->sts); @@ -91,7 +87,7 @@ * structures: A "processor generic error" that is parsed, and an IA32/X64 one * to capture complete information. */ -static void build_bert_mca_error(struct mca_bank *mci) +static void build_bert_mca_error(struct mca_bank_status *mci) { acpi_generic_error_status_t *status; acpi_hest_generic_data_v300_t *gen_entry; @@ -153,7 +149,8 @@ void check_mca(void) { int i; - struct mca_bank mci; + struct mca_bank_status mci; + msr_t msr; const unsigned int num_banks = mca_get_bank_count(); for (i = 0 ; i < num_banks ; i++) { @@ -165,18 +162,18 @@ printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(MCAX_ADDR_MSR(i)); + msr = rdmsr(MCAX_ADDR_MSR(i)); printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(MCAX_MISC0_MSR(i)); + i, msr.hi, msr.lo); + msr = rdmsr(MCAX_MISC0_MSR(i)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(MCAX_CTL_MSR(i)); + i, msr.hi, msr.lo); + msr = rdmsr(MCAX_CTL_MSR(i)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, mci.ctl.hi, mci.ctl.lo); - mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i)); + i, msr.hi, msr.lo); + msr = rdmsr(MCA_CTL_MASK_MSR(i)); printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, mci.cmask.hi, mci.cmask.lo); + i, msr.hi, msr.lo); mci.bank = i; if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) @@ -185,8 +182,8 @@ } /* zero the machine check error status registers */ - mci.sts.lo = 0; - mci.sts.hi = 0; + msr.lo = 0; + msr.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(MCAX_STATUS_MSR(i), mci.sts); + wrmsr(MCAX_STATUS_MSR(i), msr); } diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 6432ff4..4c9d9b1 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -9,13 +9,9 @@ #include <arch/bert_storage.h> #include <cper.h> -struct mca_bank { +struct mca_bank_status { int bank; - msr_t ctl; msr_t sts; - msr_t addr; - msr_t misc; - msr_t cmask; }; static inline size_t mca_report_size_reqd(void) @@ -45,7 +41,7 @@ return size; } -static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci) +static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) { int error = mca_err_type(mci->sts); @@ -63,7 +59,7 @@ /* Fill additional information in the Generic Processor Error Section. */ static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank *mci) + struct mca_bank_status *mci) { int type = mca_err_type(mci->sts); @@ -91,7 +87,7 @@ * Processor Generic section and the failing error/check added to the * IA32/X64 section. */ -static void build_bert_mca_error(struct mca_bank *mci) +static void build_bert_mca_error(struct mca_bank_status *mci) { acpi_generic_error_status_t *status; acpi_hest_generic_data_v300_t *gen_entry; @@ -152,7 +148,8 @@ void check_mca(void) { int i; - struct mca_bank mci; + struct mca_bank_status mci; + msr_t msr; const unsigned int num_banks = mca_get_bank_count(); if (is_warm_reset()) { @@ -167,18 +164,18 @@ printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(IA32_MC0_ADDR + (i * 4)); + msr = rdmsr(IA32_MC0_ADDR + (i * 4)); printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", - i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(IA32_MC0_MISC + (i * 4)); + i, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", - i, mci.misc.hi, mci.misc.lo); - mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); + i, msr.hi, msr.lo); + msr = rdmsr(IA32_MC0_CTL + (i * 4)); printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n", - i, mci.ctl.hi, mci.ctl.lo); - mci.cmask = rdmsr(MC0_CTL_MASK + i); + i, msr.hi, msr.lo); + msr = rdmsr(MC0_CTL_MASK + i); printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n", - i, mci.cmask.hi, mci.cmask.lo); + i, msr.hi, msr.lo); mci.bank = i; if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) @@ -188,8 +185,8 @@ } /* zero the machine check error status registers */ - mci.sts.lo = 0; - mci.sts.hi = 0; + msr.lo = 0; + msr.hi = 0; for (i = 0 ; i < num_banks ; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); + wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I925347dff950ac2bd021635ca988c02fba48df7f Gerrit-Change-Number: 56237 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: mark num_banks as constant
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

1 0

Change in coreboot[master]: include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56235 ) Change subject: include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC ...................................................................... include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC Those registers are architectural MSR and this also gets them in line with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are ascending. Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/x86/msr.h M src/soc/amd/stoneyridge/mca.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/56235/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 748aed5..da1932c 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -74,11 +74,11 @@ #define MCA_STATUS_LO_ERRCODE_EXT_SH 16 #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) +#define IA32_MC0_ADDR 0x402 +#define IA32_MC0_MISC 0x403 #define IA32_VMX_BASIC_MSR 0x480 #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define IA32_VMX_MISC_MSR 0x485 -#define MC0_ADDR 0x402 -#define MC0_MISC 0x403 #define MC0_CTL_MASK 0xC0010044 #define IA32_PM_ENABLE 0x770 diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 1523563..c2ec402 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -169,10 +169,10 @@ printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", i, mci.sts.hi, mci.sts.lo); - mci.addr = rdmsr(MC0_ADDR + (i * 4)); + mci.addr = rdmsr(IA32_MC0_ADDR + (i * 4)); printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n", i, mci.addr.hi, mci.addr.lo); - mci.misc = rdmsr(MC0_MISC + (i * 4)); + mci.misc = rdmsr(IA32_MC0_MISC + (i * 4)); printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n", i, mci.misc.hi, mci.misc.lo); mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4)); -- To view, visit https://review.coreboot.org/c/coreboot/+/56235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c Gerrit-Change-Number: 56235 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Use initial_lapicid() instead of open coding it
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Paul Menzel, Angel Pons, Arthur Heymans, Morgan Jang, Patrick Rudolph. Felix Held has uploaded a new patch set (#4) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55063 ) Change subject: src: Use initial_lapicid() instead of open coding it ...................................................................... src: Use initial_lapicid() instead of open coding it Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before. Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/xeon_sp/smmrelocate.c 5 files changed, 13 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55063/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Gerrit-Change-Number: 55063 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/mediatek/mt8195: Remove redundant code
by Hung-Te Lin (Code Review) 13 Jul '21

13 Jul '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56203 ) Change subject: vc/mediatek/mt8195: Remove redundant code ...................................................................... vc/mediatek/mt8195: Remove redundant code Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I10b2d3c6cb3480f9e3e3232b5ce87ecf7074bbbf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56203 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/vendorcode/mediatek/mt8195/dramc/emi.c 1 file changed, 1 insertion(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/vendorcode/mediatek/mt8195/dramc/emi.c b/src/vendorcode/mediatek/mt8195/dramc/emi.c index 0804458..6649e82 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/emi.c +++ b/src/vendorcode/mediatek/mt8195/dramc/emi.c @@ -712,22 +712,13 @@ _Static_assert(DRAMC_MAX_RK > 1, "rank number is violated"); void get_rank_size_by_emi(unsigned long long dram_rank_size[DRAMC_MAX_RK]) { - //int i; unsigned int quad_ch_ratio; - //unsigned int col_bit, row_bit; unsigned long long ch0_rank0_size, ch0_rank1_size; unsigned long long ch1_rank0_size, ch1_rank1_size; unsigned int cen_emi_conh = mt_emi_sync_read(EMI_CONH); unsigned long long dq_width; - switch (mt_get_dram_type_from_hw_trap()) { - case TYPE_LPDDR4X: - case TYPE_LPDDR4: - dq_width = 2; - break; - default: - ASSERT(0); - } + dq_width = 2; dram_rank_size[0] = 0; dram_rank_size[1] = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/56203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10b2d3c6cb3480f9e3e3232b5ce87ecf7074bbbf Gerrit-Change-Number: 56203 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block/memory: Add saving memory info API to common block
by build bot (Jenkins) (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Usha P, Andrey Petrov, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51105 ) Change subject: intel/common/block/memory: Add saving memory info API to common block ...................................................................... Patch Set 9: (34 comments) File src/soc/intel/common/block/memory/meminfo.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/872c6070_b8197666 PS9, Line 61: if (channel_info->Status != CHANNEL_PRESENT) suspicious code indentation after conditional statements Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/0b1406aa_48997681 PS9, Line 63: switch (meminfo_hob->MemoryType) { code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/8b7a79b2_2a458599 PS9, Line 63: switch (meminfo_hob->MemoryType) { please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/928195f5_67b7a412 PS9, Line 64: case MRC_DDR_TYPE_DDR3: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/03bb29fb_1d885c94 PS9, Line 64: case MRC_DDR_TYPE_DDR3: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/c0f38729_52a9ce1e PS9, Line 65: ddr_type = MEMORY_TYPE_DDR3; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/cca1749b_c1446a73 PS9, Line 65: ddr_type = MEMORY_TYPE_DDR3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/4e07c70c_675f94ad PS9, Line 66: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/1302de64_0028d933 PS9, Line 66: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/4611395f_ec70b6c0 PS9, Line 67: case MRC_DDR_TYPE_LPDDR3: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/666d06ee_e82bbd6c PS9, Line 67: case MRC_DDR_TYPE_LPDDR3: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/95a79061_8bc6e516 PS9, Line 68: ddr_type = MEMORY_TYPE_LPDDR3; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/349d5ebc_75dddb20 PS9, Line 68: ddr_type = MEMORY_TYPE_LPDDR3; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/153b8985_2e807712 PS9, Line 69: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/ad9562f2_637514f6 PS9, Line 69: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/da130b7f_c899e87c PS9, Line 70: case MRC_DDR_TYPE_DDR4: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/63fe25fd_bb45e905 PS9, Line 70: case MRC_DDR_TYPE_DDR4: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/9012f479_9b187a2e PS9, Line 71: ddr_type = MEMORY_TYPE_DDR4; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/90616158_0766dd55 PS9, Line 71: ddr_type = MEMORY_TYPE_DDR4; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/5597a329_e55f63f7 PS9, Line 72: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/2bda5304_3320be62 PS9, Line 72: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/3b9314a2_2f386894 PS9, Line 73: case MRC_DDR_TYPE_LPDDR4: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/c1a45db2_d3975dae PS9, Line 73: case MRC_DDR_TYPE_LPDDR4: please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/6faa0306_714064eb PS9, Line 74: ddr_type = MEMORY_TYPE_LPDDR4; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/5f391fba_84966164 PS9, Line 74: ddr_type = MEMORY_TYPE_LPDDR4; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/e75bc7eb_425c4057 PS9, Line 75: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/49327b59_2c5124df PS9, Line 75: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/07108369_279e88a6 PS9, Line 76: default: code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/bfb8a6a4_d0171abf PS9, Line 77: ddr_type = meminfo_hob->MemoryType; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/3a99dd4e_577ac845 PS9, Line 77: ddr_type = meminfo_hob->MemoryType; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/479aeb40_b5e2ecd4 PS9, Line 78: break; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/b66d7d9a_528e3f69 PS9, Line 78: break; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/fba3491e_f303c632 PS9, Line 79: } code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123904): https://review.coreboot.org/c/coreboot/+/51105/comment/9f430470_0be66c51 PS9, Line 79: } please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/51105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5 Gerrit-Change-Number: 51105 Gerrit-PatchSet: 9 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 01:27:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block/memory: Add saving memory info API to common block
by Bernardo Perez Priego (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Usha P, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Selma Bensaid, Tim Wawrzynczak, Subrata Banik, Usha P, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51105 to look at the new patch set (#9). Change subject: intel/common/block/memory: Add saving memory info API to common block ...................................................................... intel/common/block/memory: Add saving memory info API to common block Memory information is stored into CBMEM later to be used to generate SMBIOS table 17. This function can be part of intel common block and is available by defining SOC_INTEL_COMMON_BLOCK_MEMINFO. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5 --- A src/soc/intel/common/block/include/intelblocks/meminfo.h M src/soc/intel/common/block/memory/Kconfig M src/soc/intel/common/block/memory/Makefile.inc A src/soc/intel/common/block/memory/meminfo.c 4 files changed, 182 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/51105/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/51105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5 Gerrit-Change-Number: 51105 Gerrit-PatchSet: 9 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021