coreboot-gerrit July 2021

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Change in coreboot[master]: cpu/intel/*/*_init: use mca_get_bank_count()
by Patrick Rudolph (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Felix Held. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56244 ) Change subject: cpu/intel/*/*_init: use mca_get_bank_count() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I245b15f57e77edca179e9e28965383a227617174 Gerrit-Change-Number: 56244 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 13 Jul 2021 04:13:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG
by Dtrain Hsu (Code Review) 13 Jul '21

13 Jul '21

Dtrain Hsu has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/56248 ) Change subject: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG ...................................................................... mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG Enable/disable Touchscreen function based on Touchscreen bit of FW_CONFIG. The Touchscreen settings are included GPIO settings and I2C bus settings. BUG=b:xxxxxxxx BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb 3 files changed, 37 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/56248/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b Gerrit-Change-Number: 56248 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG
by Dtrain Hsu (Code Review) 13 Jul '21

13 Jul '21

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56248 ) Change subject: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG ...................................................................... mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG Enable/disable Touchscreen function based on Touchscreen bit of FW_CONFIG. The Touchscreen settings are included GPIO settings. BUG=b:xxxxxxxx BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb 3 files changed, 37 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/56248/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 9064297..65dd7f8 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -10,6 +10,10 @@ option DB_PORTS_1C 7 option DB_PORTS_1A_HDMI_LTE 8 end + field TOUCHSCREEN 5 + option TOUCHSCREEN_ABSENT 0 + option TOUCHSCREEN_PRESENT 1 + end field TABLETMODE 10 option TABLETMODE_DISABLED 0 option TABLETMODE_ENABLED 1 diff --git a/src/mainboard/google/dedede/variants/cret/gpio.c b/src/mainboard/google/dedede/variants/cret/gpio.c index 8cff365..9908d37 100644 --- a/src/mainboard/google/dedede/variants/cret/gpio.c +++ b/src/mainboard/google/dedede/variants/cret/gpio.c @@ -77,6 +77,21 @@ PAD_NC(GPP_D18, NONE), }; +static const struct pad_config touchscreen_disable_pads[] = { + /* A11 : TOUCH_RPT_EN */ + PAD_NC(GPP_A11, NONE), + /* D4 : TOUCH_INT_ODL */ + PAD_NC(GPP_D4, NONE), + /* D5 : TOUCH_RESET_L */ + PAD_NC(GPP_D5, NONE), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_NC(GPP_D6, NONE), + /* H4 : AP_I2C_TS_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : AP_I2C_TS_SCL */ + PAD_NC(GPP_H5, NONE), +}; + const struct pad_config *variant_override_gpio_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -85,11 +100,17 @@ static void fw_config_handle(void *unused) { + // Audio codec if (!fw_config_probe(FW_CONFIG(LTE, LTE_PRESENT))) gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_DA7219))) gpio_configure_pads(codec_da7219_pads, ARRAY_SIZE(codec_da7219_pads)); if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_CS42l42))) gpio_configure_pads(codec_cs42l42_pads, ARRAY_SIZE(codec_cs42l42_pads)); + + // Touchscreen + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_ABSENT))) + gpio_configure_pads(touchscreen_disable_pads, + ARRAY_SIZE(touchscreen_disable_pads)); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 8b26d5d..cf34db1 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -139,7 +139,9 @@ register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end + device i2c 2c on + probe TOUCHSCREEN TOUCHSCREEN_PRESENT + end end chip drivers/i2c/generic register "hid" = ""ELAN0001"" @@ -155,7 +157,9 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - device i2c 10 on end + device i2c 10 on + probe TOUCHSCREEN TOUCHSCREEN_PRESENT + end end chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" @@ -173,7 +177,9 @@ register "generic.enable_delay_ms" = "6" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 16 on end + device i2c 16 on + probe TOUCHSCREEN TOUCHSCREEN_PRESENT + end end chip drivers/i2c/hid register "generic.hid" = ""GXTP7996"" @@ -191,7 +197,9 @@ register "generic.enable_delay_ms" = "10" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end + device i2c 5d on + probe TOUCHSCREEN TOUCHSCREEN_PRESENT + end end end # I2C 2 device pci 15.3 off end # I2C 3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b Gerrit-Change-Number: 56248 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable I2C touch panel
by Bernardo Perez Priego (Code Review) 13 Jul '21

13 Jul '21

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56247 ) Change subject: mb/intel/adlrvp_m: Enable I2C touch panel ...................................................................... mb/intel/adlrvp_m: Enable I2C touch panel Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3 --- M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/gpio_m.c 2 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/56247/1 diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 34aee72..e715dab 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -212,6 +212,20 @@ end end device ref i2c0 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN7300"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)" + register "generic.enable_delay_ms" = "1" + register "generic.reset_delay_ms" = "300" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0a on end + end device ref i2c1 on chip drivers/intel/mipi_camera register "acpi_hid" = ""OVTI5675"" diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index d5eeffa..f6230cf 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -159,7 +159,14 @@ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* S7 : SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2) + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* F7 : TCH_PNL_PWR_EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* F17 : RST_N_TCH_PNL2 */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* F18 : INT_N_TCH_PNL2 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE) }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/56247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3 Gerrit-Change-Number: 56247 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] include/cpu/x86/msr: move MC0_CTL_MASK to soc/amd/stoneyridge
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56246 ) Change subject: [WIP] include/cpu/x86/msr: move MC0_CTL_MASK to soc/amd/stoneyridge ...................................................................... [WIP] include/cpu/x86/msr: move MC0_CTL_MASK to soc/amd/stoneyridge This MSR isn't an architectural MSR, so it shouldn't be in the common x86 MSR definition header file. TODO: Only stoneyridge is using this right now, but it's likely also present in other pre-Zen AMD CPUs/APUs. Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/x86/msr.h A src/soc/amd/stoneyridge/include/soc/msr.h M src/soc/amd/stoneyridge/mca.c 3 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/56246/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index dd969d7..2e0dabf 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -83,7 +83,6 @@ #define IA32_VMX_BASIC_MSR 0x480 #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define IA32_VMX_MISC_MSR 0x485 -#define MC0_CTL_MASK 0xC0010044 #define IA32_PM_ENABLE 0x770 #define IA32_HWP_CAPABILITIES 0x771 diff --git a/src/soc/amd/stoneyridge/include/soc/msr.h b/src/soc/amd/stoneyridge/include/soc/msr.h new file mode 100644 index 0000000..c51c31d --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/msr.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_STONEYRIDGE_MSR_H +#define AMD_STONEYRIDGE_MSR_H + +#define MC0_CTL_MASK 0xC0010044 + +#endif /* AMD_STONEYRIDGE_MSR_H */ diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 0773101..00e6fb9 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -5,6 +5,7 @@ #include <cpu/x86/msr.h> #include <acpi/acpi.h> #include <soc/cpu.h> +#include <soc/msr.h> #include <console/console.h> #include <arch/bert_storage.h> #include <cper.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/56246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Gerrit-Change-Number: 56246 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cpu/cpulib: use mca_get_bank_count()
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Patrick Rudolph. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56245 ) Change subject: soc/intel/common/block/cpu/cpulib: use mca_get_bank_count() ...................................................................... soc/intel/common/block/cpu/cpulib: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive, and make it constant. Change-Id: I449c74629ff16057c4559d7fd3620208230560f5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/56245/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9e95b0f..a245824 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -338,12 +338,10 @@ { msr_t msr; int i; - int num_banks; + const unsigned int num_banks = mca_get_bank_count(); printk(BIOS_DEBUG, "Clearing out pending MCEs\n"); - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; for (i = 0; i < num_banks; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I449c74629ff16057c4559d7fd3620208230560f5 Gerrit-Change-Number: 56245 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/*/*_init: use mca_get_bank_count()
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Patrick Rudolph. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56244 ) Change subject: cpu/intel/*/*_init: use mca_get_bank_count() ...................................................................... cpu/intel/*/*_init: use mca_get_bank_count() Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive, and make it constant. In the case of Intel model 2065x the mca_get_bank_count() call replaces a magic number. Change-Id: I245b15f57e77edca179e9e28965383a227617174 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c 3 files changed, 4 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/56244/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2d8bd15..29c663e 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -520,10 +520,7 @@ { msr_t msr; int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; + const unsigned int num_banks = mca_get_bank_count(); /* Enable all error reporting */ msr.lo = msr.hi = ~0; diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index abf8f61..fe5ac56 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -77,10 +77,11 @@ { msr_t msr; int i; + const unsigned int num_banks = mca_get_bank_count(); msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ - for (i = 0; i < 7; i++) + for (i = 0; i < num_banks; i++) wrmsr(IA32_MC_STATUS(i), msr); } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index bfe1fa5..541cb3b 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -301,10 +301,7 @@ { msr_t msr; int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; + const unsigned int num_banks = mca_get_bank_count(); msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I245b15f57e77edca179e9e28965383a227617174 Gerrit-Change-Number: 56244 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/cpu/x86/msr: introduce IA32_MC_*(x) macros
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Patrick Rudolph. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56243 ) Change subject: include/cpu/x86/msr: introduce IA32_MC_*(x) macros ...................................................................... include/cpu/x86/msr: introduce IA32_MC_*(x) macros When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/x86/msr.h M src/security/intel/txt/common.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/common/block/cpu/cpulib.c 11 files changed, 22 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/56243/1 diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 1bcbc34..76c8521 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -63,7 +63,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index c7fcb36..883bd59 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -62,7 +62,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 28c3e78..f945f80 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -60,7 +60,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 7266a2c..3c78c09 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -45,7 +45,7 @@ msr.lo = 0; msr.hi = 0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9fcb527..2d8bd15 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -528,14 +528,14 @@ /* Enable all error reporting */ msr.lo = msr.hi = ~0; for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_CTL + (i * 4), msr); + wrmsr(IA32_MC_CTL(i), msr); msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears * every bank. */ for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); } /* All CPUs including BSP will run the following function. */ diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index dd2aeef..abf8f61 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -81,7 +81,7 @@ msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ for (i = 0; i < 7; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); } static void model_2065x_init(struct device *cpu) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7a40644..bfe1fa5 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -309,7 +309,7 @@ msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); } static void model_206ax_report(void) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index da1932c..dd969d7 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -56,7 +56,9 @@ #define DCA_TYPE0_EN (1 << 0) #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 +#define IA32_MC_CTL(bank) (IA32_MC0_CTL + 4 * (bank)) #define IA32_MC0_STATUS 0x401 +#define IA32_MC_STATUS(bank) (IA32_MC0_STATUS + 4 * (bank)) #define MCA_STATUS_HI_VAL (1UL << (63 - 32)) #define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32)) #define MCA_STATUS_HI_UC (1UL << (61 - 32)) @@ -75,7 +77,9 @@ #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) #define IA32_MC0_ADDR 0x402 +#define IA32_MC_ADDR(bank) (IA32_MC0_ADDR + 4 * (bank)) #define IA32_MC0_MISC 0x403 +#define IA32_MC_MISC(bank) (IA32_MC0_MISC + 4 * (bank)) #define IA32_VMX_BASIC_MSR 0x480 #define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32)) #define IA32_VMX_MISC_MSR 0x485 diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 011e8cc..2b7d926 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -483,7 +483,7 @@ */ size_t max_mc_msr = mca_get_bank_count(); for (size_t i = 0; i < max_mc_msr; i++) { - msr = rdmsr(IA32_MC0_STATUS + 4 * i); + msr = rdmsr(IA32_MC_STATUS(i)); if (!(msr.hi & MCA_STATUS_HI_UC)) continue; diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 920ee7d..0773101 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -119,8 +119,7 @@ ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); if (!ctx) goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, - IA32_MC0_CTL + (mci->bank * 4), 4); + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); if (!ctx) goto failed; ctx = cper_new_ia32x64_context_msr(status, x86_sec, @@ -152,13 +151,13 @@ printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, mca_bank_name[bank]); - msr = rdmsr(IA32_MC0_STATUS + (bank * 4)); + msr = rdmsr(IA32_MC_STATUS(bank)); printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_ADDR + (bank * 4)); + msr = rdmsr(IA32_MC_ADDR(bank)); printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_MISC + (bank * 4)); + msr = rdmsr(IA32_MC_MISC(bank)); printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC0_CTL + (bank * 4)); + msr = rdmsr(IA32_MC_CTL(bank)); printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); msr = rdmsr(MC0_CTL_MASK + bank); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); @@ -177,7 +176,7 @@ continue; mci.bank = i; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); + mci.sts = rdmsr(IA32_MC_STATUS(i)); if (mci.sts.hi || mci.sts.lo) { mca_print_error(i); @@ -194,7 +193,7 @@ /* Zero all machine check error status registers */ for (unsigned int i = 0 ; i < num_banks ; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); } void check_mca(void) diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 81e42ae..9e95b0f 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -348,9 +348,9 @@ for (i = 0; i < num_banks; i++) { /* Clear the machine check status */ - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Initialize machine checks */ - wrmsr(IA32_MC0_CTL + i * 4, + wrmsr(IA32_MC_CTL(i), (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/56243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Gerrit-Change-Number: 56243 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/mca: refactor warm boot check in mca_check_all_banks
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56242 ) Change subject: soc/amd/stoneyridge/mca: refactor warm boot check in mca_check_all_banks ...................................................................... soc/amd/stoneyridge/mca: refactor warm boot check in mca_check_all_banks Change-Id: Id0cf8269d1b695e05c55f33af92978b8244090fa Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/mca.c 1 file changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/56242/1 diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 9ba201e..920ee7d 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -169,19 +169,20 @@ struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); - if (is_warm_reset()) { - for (unsigned int i = 0 ; i < num_banks ; i++) { - if (i == 3) /* Reserved in Family 15h */ - continue; + if (!is_warm_reset()) + return; - mci.bank = i; - mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); - if (mci.sts.hi || mci.sts.lo) { - mca_print_error(i); + for (unsigned int i = 0 ; i < num_banks ; i++) { + if (i == 3) /* Reserved in Family 15h */ + continue; - if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } + mci.bank = i; + mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); + if (mci.sts.hi || mci.sts.lo) { + mca_print_error(i); + + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) + build_bert_mca_error(&mci); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/56242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0cf8269d1b695e05c55f33af92978b8244090fa Gerrit-Change-Number: 56242 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso,stoneyridge/mca: factor out mca_check_all_banks
by Felix Held (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56241 ) Change subject: soc/amd/picasso,stoneyridge/mca: factor out mca_check_all_banks ...................................................................... soc/amd/picasso,stoneyridge/mca: factor out mca_check_all_banks Change-Id: I5496fd27f5c56d35ab95a5e02ea313b5b5536668 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 34 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/56241/1 diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 7561a56..973b3b5 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -164,6 +164,23 @@ printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } +static void mca_check_all_banks(void) +{ + struct mca_bank_status mci; + const unsigned int num_banks = mca_get_bank_count(); + + for (unsigned int i = 0 ; i < num_banks ; i++) { + mci.bank = i; + mci.sts = rdmsr(MCAX_STATUS_MSR(i)); + if (mci.sts.hi || mci.sts.lo) { + mca_print_error(i); + + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) + build_bert_mca_error(&mci); + } + } +} + static void mca_clear_errors(void) { const unsigned int num_banks = mca_get_bank_count(); @@ -177,20 +194,6 @@ /* Check the Machine Check Architecture Extension registers */ void check_mca(void) { - unsigned int i; - struct mca_bank_status mci; - const unsigned int num_banks = mca_get_bank_count(); - - for (i = 0 ; i < num_banks ; i++) { - mci.bank = i; - mci.sts = rdmsr(MCAX_STATUS_MSR(i)); - if (mci.sts.hi || mci.sts.lo) { - mca_print_error(i); - - if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } - } - + mca_check_all_banks(); mca_clear_errors(); } diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index a64b01d..9ba201e 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -164,24 +164,13 @@ printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } -static void mca_clear_errors(void) +static void mca_check_all_banks(void) { - const unsigned int num_banks = mca_get_bank_count(); - const msr_t msr = {.lo = 0, .hi = 0}; - - /* Zero all machine check error status registers */ - for (unsigned int i = 0 ; i < num_banks ; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); -} - -void check_mca(void) -{ - unsigned int i; struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); if (is_warm_reset()) { - for (i = 0 ; i < num_banks ; i++) { + for (unsigned int i = 0 ; i < num_banks ; i++) { if (i == 3) /* Reserved in Family 15h */ continue; @@ -195,6 +184,20 @@ } } } +} +static void mca_clear_errors(void) +{ + const unsigned int num_banks = mca_get_bank_count(); + const msr_t msr = {.lo = 0, .hi = 0}; + + /* Zero all machine check error status registers */ + for (unsigned int i = 0 ; i < num_banks ; i++) + wrmsr(IA32_MC0_STATUS + (i * 4), msr); +} + +void check_mca(void) +{ + mca_check_all_banks(); mca_clear_errors(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5496fd27f5c56d35ab95a5e02ea313b5b5536668 Gerrit-Change-Number: 56241 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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