coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: soc/skylake: Make VT-d controllable from CMOS option
by Sean Rhodes (Code Review) 13 Jul '21

13 Jul '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56252 ) Change subject: soc/skylake: Make VT-d controllable from CMOS option ...................................................................... soc/skylake: Make VT-d controllable from CMOS option Make VT-d enable or disable based on CMOS value "vtd" 1 = Enable 0 = Disable Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1aea14968e08ee6af822bd259ca1d462f8926994 --- M src/soc/intel/skylake/chip.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/56252/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 2599e12..1f2e8f8 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -9,6 +9,7 @@ #include <device/pci_ids.h> #include <fsp/util.h> #include <gpio.h> +#include <option.h> #include <intelblocks/cfg.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> @@ -18,6 +19,7 @@ #include <intelblocks/xdci.h> #include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> +#include <limits.h> #include <soc/acpi.h> #include <soc/intel/common/vbt.h> #include <soc/interrupt.h> @@ -29,6 +31,7 @@ #include <soc/systemagent.h> #include <soc/usb.h> #include <string.h> +#include <types.h> #include "chip.h" @@ -501,11 +504,12 @@ params->PchIoApicBdfValid = 0; /* Enable VT-d and X2APIC */ + const unsigned int vtd = get_uint_option("vtd", 1); if (soc_is_vtd_capable()) { params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; params->X2ApicOptOut = 0; - tconfig->VtdDisable = 0; + tconfig->VtdDisable = !vtd; } params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); -- To view, visit https://review.coreboot.org/c/coreboot/+/56252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aea14968e08ee6af822bd259ca1d462f8926994 Gerrit-Change-Number: 56252 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya: DSM setting enablement for Intel WLAN card
by Ravindra (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak. Ravindra has removed Ravindra N from this change. ( https://review.coreboot.org/c/coreboot/+/56249 ) Change subject: mb/google/brya: DSM setting enablement for Intel WLAN card ...................................................................... Removed reviewer Ravindra N. -- To view, visit https://review.coreboot.org/c/coreboot/+/56249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22411ca8648e89397a2c8dab6ed9041f47c664b8 Gerrit-Change-Number: 56249 Gerrit-PatchSet: 4 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: deleteReviewer

1 0

Change in coreboot[master]: mb/google/brya: DSM setting enablement for Intel WLAN card
by Ravindra (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Rizwan Qureshi, Tim Wawrzynczak. Ravindra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56249 ) Change subject: mb/google/brya: DSM setting enablement for Intel WLAN card ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Please review the changes -- To view, visit https://review.coreboot.org/c/coreboot/+/56249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22411ca8648e89397a2c8dab6ed9041f47c664b8 Gerrit-Change-Number: 56249 Gerrit-PatchSet: 4 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 06:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/wifi/generic: DSM setting enablement for Intel WLAN card
by build bot (Jenkins) (Code Review) 13 Jul '21

13 Jul '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56251 ) Change subject: drivers/wifi/generic: DSM setting enablement for Intel WLAN card ...................................................................... Patch Set 1: (2 comments) File src/drivers/wifi/generic/acpi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123929): https://review.coreboot.org/c/coreboot/+/56251/comment/fde3c1f7_30567187 PS1, Line 47: void wifi_write_dsm(const char *uuid, void (**callbacks)(void *), function definition argument 'void' should also have an identifier name Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123929): https://review.coreboot.org/c/coreboot/+/56251/comment/9d53f6be_a4124456 PS1, Line 47: void wifi_write_dsm(const char *uuid, void (**callbacks)(void *), function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/56251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62f4be846ffb83ea6eaed5a83440bc035b401425 Gerrit-Change-Number: 56251 Gerrit-PatchSet: 1 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 06:23:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/wifi/generic: DSM setting enablement for Intel WLAN card
by Ravindra (Code Review) 13 Jul '21

13 Jul '21

Ravindra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56251 ) Change subject: drivers/wifi/generic: DSM setting enablement for Intel WLAN card ...................................................................... drivers/wifi/generic: DSM setting enablement for Intel WLAN card To support worldwide regulatory WLAN feature(Indonesia AX / Ukraine AX / Russia AX), Intel WLAN card has to set DSM setting to meet the regulatory requirement which allows to modify the settings. BUG=none TEST=Generate SSDT tables and verify the required settings applied Signed-off-by: Ravindra <ravindra(a)intel.com> Change-Id: I62f4be846ffb83ea6eaed5a83440bc035b401425 --- M src/drivers/wifi/generic/acpi.c 1 file changed, 144 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/56251/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 3e3b5c1..46d9a42 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <sar.h> #include <wrdd.h> +#include <include/fw_config.h> #include "chip.h" #include "wifi_private.h" @@ -34,6 +35,143 @@ */ #define WIFI_ACPI_NAME_MAX_LEN 5 +/* Unique ID for the WIFI _DSM. */ +#define ACPI_DSM_OEM_WIFI_UUID "F21202BF-8F78-4DC6-A5B3-1F738E285ADE" + +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + */ +void wifi_write_dsm(const char *uuid, void (**callbacks)(void *), + size_t count, void *arg); +void wifi_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count); +static void wifi_write_dsm_uuid(struct dsm_uuid *id); + +/* + * Function 2 : Supported Indonesia 5.15-5.35 GHz Band + * 00 - Set 5.115-5.35GHz to Disable in Indonesia + * 01 - Set 5.115-5.35GHz to Enable (Passive) in Indonesia + * 02 - Reserved + */ +static void wifi_dsm_indonasia_5Ghz_band_enable(void *arg) +{ + bool band_5ghz_enabled = fw_config_probe(FW_CONFIG(WIFI_INDONESIA_5GHZ_CONFIG, + BAND_5GHZ_ENABLE)); + acpigen_write_to_integer(band_5ghz_enabled, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_write_return_integer(1); + acpigen_write_else(); + acpigen_write_return_integer(0); + acpigen_pop_len(); +} + +/* + * Function 6: 11Ax Control + * Bit 0 - Apply changes to country Ukraine. 11Ax Setting within + * module certification + * 0 - None. Work with Wi-Fi FW/OTP definitions [Default] + * 1 - Apply changes. + * + * Bit 1 - 11Ax Mode. Effective only if Bit 0 set to 1 + * 0 - Disable 11Ax on country Ukraine [Default] + * 1 - Enable 11Ax on country Ukraine + * + * Bit 2 - Apply changes to country Russia. 11Ax Setting within + * module certification + * 0 - None. Work with Wi-Fi FW/OTP definitions [Default] + * 1 - Apply changes. + * + * Bit 3 - 11Ax Mode. Effective only if Bit 2 set to 1 + * 0 - Disable 11Ax on country Russia [Default] + * 1 - Enable 11Ax on country Russia + * + * Bit 31:04 - Reserved + * + */ +static void wifi_dsm_ukrane_russia_11ax_enable(void *arg) +{ + bool dsm_11ax_enabled = fw_config_probe(FW_CONFIG(WIFI_OTP_DEF, + UKR_RUS_OTP_11AX_DEFAULT)); + acpigen_write_to_integer(dsm_11ax_enabled, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_write_return_singleton_buffer(0x0000); + acpigen_pop_len(); + dsm_11ax_enabled = fw_config_probe(FW_CONFIG(WIFI_OTP_DEF, + UKR_OTP_ENB_11AX_ENB)); + acpigen_write_to_integer(dsm_11ax_enabled, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_write_return_singleton_buffer(0x0011); + acpigen_pop_len(); + dsm_11ax_enabled = fw_config_probe(FW_CONFIG(WIFI_OTP_DEF, + UKR_OTP_ENB_11AX_DIS)); + acpigen_write_to_integer(dsm_11ax_enabled, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_write_return_singleton_buffer(0x0010); + acpigen_pop_len(); +} + +static void (*wifi_dsm_callbacks[])(void *) = { + NULL, /* Function 0 */ + NULL, /* Function 1 */ + wifi_dsm_indonasia_5Ghz_band_enable, /* Function 2 */ + NULL, /* Function 3 */ + NULL, /* Function 4 */ + NULL, /* Function 5 */ + wifi_dsm_ukrane_russia_11ax_enable, /* Function 6 */ +}; + +void wifi_write_dsm(const char *uuid, void (**callbacks)(void *), + size_t count, void *arg) +{ + struct dsm_uuid id = DSM_UUID(uuid, callbacks, count, arg); + wifi_write_dsm_uuid_arr(&id, 1); +} + +static void wifi_write_dsm_uuid(struct dsm_uuid *id) +{ + size_t i; + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid(id->uuid); + + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + + for (i = 0; i < id->count; i++) { + /* If (LEqual (Local1, i)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, i); + + /* Callback to write if handler. */ + if (id->callbacks[i]) + id->callbacks[i](id->arg); + + acpigen_pop_len(); /* If */ + } + + acpigen_pop_len(); /* If (LEqual (Local0, ToUUID(uuid))) */ +} + +void wifi_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count) +{ + size_t i; + + /* Method (_DSM, 4, Serialized) */ + acpigen_write_method_serialized("_DSM", 0x4) + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + + for (i = 0; i < count; i++) + wifi_write_dsm_uuid(&ids[i]); + + acpigen_pop_len(); /* Method _DSM */ +} + __weak int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) { return -1; @@ -183,10 +321,15 @@ static void wifi_ssdt_write_properties(const struct device *dev, const char *scope) { const struct drivers_wifi_generic_config *config = dev->chip_info; - /* Scope */ acpigen_write_scope(scope); + /* Call Wifi DSM method */ + wifi_write_dsm(ACPI_DSM_OEM_WIFI_UUID, + wifi_dsm_callbacks, + ARRAY_SIZE(wifi_dsm_callbacks), + NULL); + /* Wake capabilities */ if (config) acpigen_write_PRW(config->wake, ACPI_S3); -- To view, visit https://review.coreboot.org/c/coreboot/+/56251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62f4be846ffb83ea6eaed5a83440bc035b401425 Gerrit-Change-Number: 56251 Gerrit-PatchSet: 1 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya: DSM setting enablement for Intel WLAN card
by Ravindra (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Tim Wawrzynczak, Ravindra, Ravindra N. Hello build bot (Jenkins), Tim Wawrzynczak, Ravindra N, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56249 to look at the new patch set (#4). Change subject: mb/google/brya: DSM setting enablement for Intel WLAN card ...................................................................... mb/google/brya: DSM setting enablement for Intel WLAN card To support worldwide regulatory WLAN feature(Indonesia AX / Ukraine AX / Russia AX), Intel WLAN card has to set DSM setting to meet the regulatory requirement which allows to modify the settings. BUG=none TEST=Generate SSDT tables and verify the required settings applied Change-Id: I22411ca8648e89397a2c8dab6ed9041f47c664b8 Signed-off-by: Ravindra <ravindra(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/56249/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22411ca8648e89397a2c8dab6ed9041f47c664b8 Gerrit-Change-Number: 56249 Gerrit-PatchSet: 4 Gerrit-Owner: Ravindra <ravindra(a)intel.com> Gerrit-Reviewer: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ravindra <ravindra(a)intel.com> Gerrit-Attention: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/intel/adlrvp: Fix Tmode setting for ADL P RVP
by Sathya Prakash M R (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Sugnan Prabhu S, Subrata Banik, Meera Ravindranath. Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56208 ) Change subject: mb/intel/adlrvp: Fix Tmode setting for ADL P RVP ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Verified on ADL P RVP -- To view, visit https://review.coreboot.org/c/coreboot/+/56208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33 Gerrit-Change-Number: 56208 Gerrit-PatchSet: 1 Gerrit-Owner: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 06:13:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: Fix Tmode setting for ADL P RVP
by Sathya Prakash M R (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Furquan Shaikh, Sugnan Prabhu S, Subrata Banik, Meera Ravindranath. Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56208 ) Change subject: mb/intel/adlrvp: Fix Tmode setting for ADL P RVP ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/56208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33 Gerrit-Change-Number: 56208 Gerrit-PatchSet: 1 Gerrit-Owner: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jul 2021 06:13:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/google/herobrine: Configure SDCC clock
by Sajida Bhanu (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Sajida Bhanu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50585 ) Change subject: mainboard/google/herobrine: Configure SDCC clock ...................................................................... Patch Set 53: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50585/comment/b93b63d1_80c895a7 PS51, Line 9: Configure clocks for eMMC and SD card > Please document the exact values here. Sure -- To view, visit https://review.coreboot.org/c/coreboot/+/50585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8acbce58614add0228adc39289762da10937cbe2 Gerrit-Change-Number: 50585 Gerrit-PatchSet: 53 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 13 Jul 2021 06:07:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG
by Dtrain Hsu (Code Review) 13 Jul '21

13 Jul '21

Attention is currently required from: Dtrain Hsu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56248 to look at the new patch set (#3). Change subject: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG ...................................................................... mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG Enable/disable Touchscreen function based on Touchscreen bit of FW_CONFIG. The Touchscreen settings are included GPIO settings and I2C bus settings. BUG=b:193482999 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb 3 files changed, 37 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/56248/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b Gerrit-Change-Number: 56248 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021