coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7180: Renaming the GPIO macro in QSPI and I2C driver
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56194 ) Change subject: sc7180: Renaming the GPIO macro in QSPI and I2C driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51eedc722a91c5ea8e009fb8468a60667d374b49 Gerrit-Change-Number: 56194 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:45:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add target specific GPIO pin definitions
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, Taniya Das, Julius Werner, mturney mturney. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55079 ) Change subject: sc7180: Add target specific GPIO pin definitions ...................................................................... Patch Set 13: (1 comment) File src/soc/qualcomm/sc7180/include/soc/gpio.h: https://review.coreboot.org/c/coreboot/+/55079/comment/f3533ab2_b2f2c4b0 PS13, Line 11: 0x1000 Why did we get rid of this macro? Are they not equivalent? -- To view, visit https://review.coreboot.org/c/coreboot/+/55079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268 Gerrit-Change-Number: 55079 Gerrit-PatchSet: 13 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:44:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: get boardid from GPIO configuration
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55950 ) Change subject: herobrine: get boardid from GPIO configuration ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/herobrine/boardid.c: https://review.coreboot.org/c/coreboot/+/55950/comment/51288241_418ff0aa PS5, Line 25: CB_ERR Can CB_ERR be interpreted as an actual board_id? Should we just return UNDEFINED_STRAPPING_ID instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/55950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4 Gerrit-Change-Number: 55950 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:42:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src: Use initial_lapicid() instead of open coding it
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Paul Menzel, Angel Pons, Arthur Heymans, Morgan Jang, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55063 ) Change subject: src: Use initial_lapicid() instead of open coding it ...................................................................... Patch Set 3: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55063/comment/418920e6_edac94ed PS1, Line 7: use > I'd also add a prefix: […] Done https://review.coreboot.org/c/coreboot/+/55063/comment/aa0141f8_6fbc6968 PS1, Line 7: opencoding > I believe `open coding` is spelled with a space Done File src/drivers/amd/agesa/eventlog.c: https://review.coreboot.org/c/coreboot/+/55063/comment/6ae72f3a_be797144 PS1, Line 101: task->apic_id = (u8)initial_lapicid(); > Would this work in x2APIC mode? hm, good question. does the old agesa code support x2apic anyway? File src/drivers/amd/agesa/romstage.c: https://review.coreboot.org/c/coreboot/+/55063/comment/1bcdd957_3da08726 PS1, Line 39: u32 > `unsigned int` Done File src/soc/amd/picasso/mca.c: https://review.coreboot.org/c/coreboot/+/55063/comment/8d8afdbd_7143b7be PS2, Line 167: int > See my comments on earlier patchsets. […] Done File src/soc/amd/stoneyridge/mca.c: https://review.coreboot.org/c/coreboot/+/55063/comment/d05e81f2_0c9e69f8 PS1, Line 169: uint32_t > `initial_lapicid()` returns `unsigned int`. […] Done https://review.coreboot.org/c/coreboot/+/55063/comment/198b744f_40634fea PS1, Line 171: %d > Needs to be changed to `%u` now that `core` is of unsigned type. […] Done File src/soc/intel/xeon_sp/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/55063/comment/e4ccd59a_39060418 PS1, Line 90: int apic_id; > This can be removed now. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Gerrit-Change-Number: 55063 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:29:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src: Use initial_lapicid() instead of open coding it
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Arthur Heymans, Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Paul Menzel, Morgan Jang, Patrick Rudolph, Felix Held. Felix Held has uploaded a new patch set (#3) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55063 ) Change subject: src: Use initial_lapicid() instead of open coding it ...................................................................... src: Use initial_lapicid() instead of open coding it Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before. Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/xeon_sp/smmrelocate.c 5 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55063/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Gerrit-Change-Number: 55063 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table
by Tim Wawrzynczak (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56175 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ...................................................................... soc/intel/alderlake: Add (and fix) devices in IRQ table Some devices were missing from the IRQ table, and this lack of IRQ programming for the devices (although unused), was causing S0ix entry to fail. BUG=b:176858827 TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle correctly upon entry/exit from S0ix Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 51 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/56175/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Gerrit-Change-Number: 56175 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/google/herobrine: Configure SDCC clock
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50585 ) Change subject: mainboard/google/herobrine: Configure SDCC clock ...................................................................... Patch Set 53: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8acbce58614add0228adc39289762da10937cbe2 Gerrit-Change-Number: 50585 Gerrit-PatchSet: 53 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:25:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by Julian Schroeder (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56188 ) Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... Patch Set 4: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56188/comment/26be41cf_37c6820f PS2, Line 7: > i'd add an "add" here Done https://review.coreboot.org/c/coreboot/+/56188/comment/fc8bb1b5_1c986c8b PS2, Line 9: CPPC > might be good to have the acronym expanded in the commit message text. […] Done Patchset: PS4: I think I addressed all of Felix' comments... File src/soc/amd/cezanne/cppc.h: PS2: > this one should probably be moved to src/soc/amd/cezanne/include/soc/cppc. […] Done File src/soc/amd/cezanne/cppc_init.c: PS2: > i'd move the contents of this file to cppc.c. […] Done https://review.coreboot.org/c/coreboot/+/56188/comment/31428efa_baed034c PS2, Line 33: msr.addrl = 0xc00102b0; > would be good to have defines for those instead of the magic msr numbers here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 4 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:23:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by Julian Schroeder (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julian Schroeder. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56188 to look at the new patch set (#4). Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... soc/amd/cezanne: add ACPI CPPC support for AMD CollaborativeProcessorPerformanceControl See also: uefi.org/specifications This leverages the existing CPPC support and adds a cppc init for AMD/Cezanne. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/acpi.c A src/soc/amd/cezanne/cppc.c A src/soc/amd/cezanne/include/soc/cppc.h 4 files changed, 215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 4 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by build bot (Jenkins) (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56188 ) Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/cppc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123883): https://review.coreboot.org/c/coreboot/+/56188/comment/41989588_c0f0ac86 PS3, Line 18: .access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS, //4 trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 3 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:18:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2021