coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by Julian Schroeder (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julian Schroeder. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56188 to look at the new patch set (#3). Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... soc/amd/cezanne: add ACPI CPPC support for AMD CollaborativeProcessorPerformanceControl See also: uefi.org/specifications This leverages the existing CPPC support and adds a cppc init for AMD/Cezanne. Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/acpi.c A src/soc/amd/cezanne/cppc.c A src/soc/amd/cezanne/include/soc/cppc.h 4 files changed, 214 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 3 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56088 ) Change subject: mainboard: Add Star Labs labtop series ...................................................................... Patch Set 16: (1 comment) File src/mainboard/starlabs/labtop/variants/tgl/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123882): https://review.coreboot.org/c/coreboot/+/56088/comment/b63f903a_3dbe4401 PS16, Line 45: memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated);d; space required after that ';' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/56088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Gerrit-Change-Number: 56088 Gerrit-PatchSet: 16 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Mon, 12 Jul 2021 19:07:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table
by Tim Wawrzynczak (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56175 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table ...................................................................... soc/intel/alderlake: Add (and fix) devices in IRQ table Some devices were missing from the IRQ table, and this lack of IRQ programming for the devices (although unused), was causing S0ix entry to fail. BUG=b:176858827 TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle correctly upon entry/exit from S0ix Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 50 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/56175/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Gerrit-Change-Number: 56175 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/external/tianocore: Add build argument for 4G Decode
by Sean Rhodes (Code Review) 12 Jul '21

12 Jul '21

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56223 ) Change subject: payloads/external/tianocore: Add build argument for 4G Decode ...................................................................... payloads/external/tianocore: Add build argument for 4G Decode Add Kconfig option TIANOCORE_DISABLE_ABOVE_4G to pass build option to edk2 to disable "Above 4G Decode". Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ia3b1d15196c0ec611431af29031682fea626d19d --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/56223/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 3d46553..9e626cb 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -147,6 +147,7 @@ CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \ CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \ CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \ + CONFIG_TIANOCORE_DISABLE_ABOVE_4G=$(TIANOCORE_DISABLE_ABOVE_4G) \ CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \ CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index cb3ff5d..e4ecdae 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -92,4 +92,10 @@ For boards with an internal display, the default value of 2s is generally sufficient. For boards without an internal display, a value of 5s is generally sufficient. +config TIANOCORE_DISABLE_ABOVE_4G + string "Disable Above 4G Decode" + help + Disable Above 4G Decode so that the DXE core only dispatches drivers below 4GB. Required + for Qubes (Xen). + endif diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 92a809a..336d0c0 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -34,9 +34,13 @@ CBMEM=-D USE_CBMEM_FOR_CONSOLE=TRUE endif +ifeq ($(CONFIG_TIANOCORE_DISABLE_ABOVE_4G),y) +4G=-D ABOVE_4G_ENABLE=FALSE +endif + TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) -BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) +BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G) all: clean build -- To view, visit https://review.coreboot.org/c/coreboot/+/56223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b1d15196c0ec611431af29031682fea626d19d Gerrit-Change-Number: 56223 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/sc7280: Replace gpio offset value with macro
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, Taniya Das. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55949 ) Change subject: soc/qualcomm/sc7280: Replace gpio offset value with macro ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364 Gerrit-Change-Number: 55949 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 18:25:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common/gpio: Define a macro for the gpio offset
by Shelley Chen (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Ravi kumar, Taniya Das. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55948 ) Change subject: soc/qualcomm/common/gpio: Define a macro for the gpio offset ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65 Gerrit-Change-Number: 55948 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 18:24:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in
by Cliff Huang (Code Review) 12 Jul '21

12 Jul '21

Cliff Huang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55127 ) Change subject: soc/intel/common/acpi: add ACPI S0ix _DSM for Intel Power Engine Plug-in ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991662cbebf63bd71139ed37ff2588ba73f30398 Gerrit-Change-Number: 55127 Gerrit-PatchSet: 12 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sukumar Ghorai <sukumar.ghorai(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP
by Cliff Huang (Code Review) 12 Jul '21

12 Jul '21

Cliff Huang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55150 ) Change subject: soc/intel/alderlake: enable ACPI S0ix DSM for Intel PEP ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I127c695eed9e2842996381c7559695f289cf4585 Gerrit-Change-Number: 55150 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP
by Cliff Huang (Code Review) 12 Jul '21

12 Jul '21

Cliff Huang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55151 ) Change subject: soc/intel/tigerlake: enable ACPI S0ix DSM for Intel PEP ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/55151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87fa55e4003e789d55ddce11d1f76e9ca8b08f18 Gerrit-Change-Number: 55151 Gerrit-PatchSet: 5 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
by Cliff Huang (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph, Karthik Ramasubramanian. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56005 ) Change subject: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b Gerrit-Change-Number: 56005 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 18:09:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2021