coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine
by Cliff Huang (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56006 ) Change subject: soc/intel/alderlake: Switch to runtime generation of Intel Power Engine ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/pmc.c: https://review.coreboot.org/c/coreboot/+/56006/comment/8f764f7a_899579ba PS1, Line 126: /* Add Intel Power Engine device */ > If SOC_INTEL_COMMON_BLOCK_ACPI_PEP is unselected temporary for some test reason, this line also need […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Gerrit-Change-Number: 56006 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 18:08:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Nikolai Vyssotski (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Marshall Dawson, Andrey Petrov, Patrick Rudolph. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 2: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/56190/comment/e843aed2_22e9f7a3 PS2, Line 13: however, some FSP 2.0 variants have it as well. > Then it is not conforming to FSP specification: […] I agree with you. I prefer it not going into coreboot either. Martin and I discussed this in great detail. It does violate Intel's FSP 2.0 spec - this is what I tried to highlight in the comment. However the fact remains - the current implementations of FSP 2.0 header in edk2 have FspMultiPhaseSiInitEntryOffset field in there (see https://github.com/tianocore/edk2/blob/master/IntelFsp2Pkg/Include/Guid/Fsp… and https://bugzilla.tianocore.org/show_bug.cgi?id=2698). It is not only in FSP 2.2 but also in FSP 2.0 header now (since commit f2cdb268 by hasel.chiu(a)intel.com on Apr 30 2020). FSP version supported by edk2 is defined in IntelFsp2Pkg/IntelFsp2Pkg.dec by PcdFspHeaderSpecVersion, which is still at 0x20 or FSP 2.0. If we want to upgrade from UDK2018 to anything more recent than stable202005 we will need to accommodate it in coreboot. The other option is to override this header file during FSP build but per discussion with Martin it seems to be a less desirable approach. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 18:03:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: Move pep.asl to acpigen
by Cliff Huang (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph, Karthik Ramasubramanian. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56004 ) Change subject: soc/intel/common/block/acpi: Move pep.asl to acpigen ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83722e0ed5792e338fc5c39a57eef43b7464e3b Gerrit-Change-Number: 56004 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 12 Jul 2021 17:39:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" This reverts commit ce0e2a014009390c4527e064efb59260ef4d3a3b which was originally introduced as a workaround for the bug that the Linux kernel doesn't know what to do with type 16 memory region in the e820 table where CBMEM resides and disallowed accessing it. After depthcharge was patched to mark the type 16 region as a normal reserved region, the Linux kernel now can access the BERT region and print BERT errors. When SeaBIOS was used as payload it already marked the memory region correctly, so it already worked in that case. After commit 8c3a8df1021b8a2789c2a285557401837f9fc2b8 that removed the usage of the BERT memory region reserved by the FSP driver by the AMD Picasso and Cezanne SoCs and made them use CBMEM for the BERT region, no other SoC code uses this functionality. The Intel Alderlake and Tigerlake SoCs put the BERT region in CBMEM and never used this reserved memory region and the change for the Intel server CPU to use this was abandoned and never landed in upstream coreboot. AMD Stoneyridge is the only other SoC/chipset that selects ACPI_BERT, but since it doesn't select or use the FSP driver, it also won't be affected by this change. TEST=Behavior of the BERT code doesn't change on Mandolin Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56163 Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/fsp2_0/cbmem.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 2 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Arthur Heymans: Looks good to me, approved Raul Rangel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Jonathan Zhang: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 5388b89..0efb462 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -6,14 +6,7 @@ void *cbmem_top_chipset(void) { struct range_entry tolum; - uint8_t *tolum_base; fsp_find_bootloader_tolum(&tolum); - tolum_base = (uint8_t *)(uintptr_t)range_entry_base(&tolum); - - /* - * The TOLUM range may have other memory regions (such as APEI - * BERT region on top of CBMEM (IMD root and IMD small) region. - */ - return tolum_base + cbmem_overhead_size(); + return (void *)(uintptr_t)range_entry_end(&tolum); } diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index 9bfb0f1..ec526e8 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,16 +43,9 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (!CONFIG(ACPI_BERT) && range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } - - if (CONFIG(ACPI_BERT) && - range_entry_end(&tolum) != (uintptr_t)cbmem_top() + CONFIG_ACPI_BERT_SIZE) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top + 0x%x: BERT\n", - range_entry_end(&tolum), cbmem_top(), CONFIG_ACPI_BERT_SIZE); - die("Space between cbmem_top and APEI BERT!\n"); - } } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b12229d..0c9fe97 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -266,21 +266,6 @@ /* Reserve enough memory under TOLUD to save CBMEM header */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); - /* - * If ACPI APEI BERT region size is defined, reserve memory for it. - * +------------------------+ range_entry_top(tolum) - * | Other reserved regions | - * | APEI BERT region | - * +------------------------+ cbmem_top() - * | CBMEM IMD ROOT | - * | CBMEM IMD SMALL | - * +------------------------+ range_entry_base(tolum), TOLUM - * | CBMEM FSP MEMORY | - * | Other CBMEM regions... | - */ - if (CONFIG(ACPI_BERT)) - arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE; - /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rocky Phagura Gerrit-MessageType: merged

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory re...
by Felix Held (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Arthur Heymans, Rocky Phagura, Subrata Banik, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56163 ) Change subject: Revert "drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region" ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/hob_verify.c: https://review.coreboot.org/c/coreboot/+/56163/comment/954854fb_e14d1c4b PS1, Line 52: > tl;dr there is nothing to check if we do not ask the FSP to increase bootloader TOLUM size. yes, there's nothing to verify there any more. since this is a direct revert of the workaround, it restores the state before this was introduced -- To view, visit https://review.coreboot.org/c/coreboot/+/56163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca095ca327cbf925edb59b89fff42ff9f96de5d Gerrit-Change-Number: 56163 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rocky Phagura Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 17:33:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Rocky Phagura Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/kblrvp: Always use `CHIPSET_LOCKDOWN_COREBOOT`
by Angel Pons (Code Review) 12 Jul '21

12 Jul '21

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52095 ) Change subject: mb/intel/kblrvp: Always use `CHIPSET_LOCKDOWN_COREBOOT` ...................................................................... Abandoned Stuck in review, and superseded by CB:56212 -- To view, visit https://review.coreboot.org/c/coreboot/+/52095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2db1456d1734b2c0a6019002c211f608bcdf4a19 Gerrit-Change-Number: 52095 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/lib/fmap.c: use le*toh() functions where needed
by Krystian Hebel (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Angel Pons, Julius Werner. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55038 ) Change subject: src/lib/fmap.c: use le*toh() functions where needed ...................................................................... Patch Set 1: (1 comment) File src/lib/fmap.c: https://review.coreboot.org/c/coreboot/+/55038/comment/8b92174b_4f9ead2d PS1, Line 239: ar->offset, ar->size, area->name); > I suppose accesses like these need to be updated, too? This function is not called anywhere in the code currently, and I assumed that the data passed to it would already be in host endianness. (sorry for the delay, I keep forgetting to hit reply button) -- To view, visit https://review.coreboot.org/c/coreboot/+/55038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8784ac29101531db757249496315f43e4008de4f Gerrit-Change-Number: 55038 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Jul 2021 17:08:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/kblrvp/variants: Fix indentation and remove empty lines
by Angel Pons (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56211 ) Change subject: mb/intel/kblrvp/variants: Fix indentation and remove empty lines ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a Gerrit-Change-Number: 56211 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Mon, 12 Jul 2021 17:08:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/kblrvp: Move lockdown config to baseboard devicetree
by Felix Singer (Code Review) 12 Jul '21

12 Jul '21

Attention is currently required from: Felix Singer. Hello build bot (Jenkins), Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56212 to look at the new patch set (#2). Change subject: intel/kblrvp: Move lockdown config to baseboard devicetree ...................................................................... intel/kblrvp: Move lockdown config to baseboard devicetree Clean up lockdown configuration and move it to the baseboard's devicetree. Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it for the rvp8 variant for consistency as well. Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains identical. intel/rvp8 changes, as expected. Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb 4 files changed, 4 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/56212/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651 Gerrit-Change-Number: 56212 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/kblrvp/variants: Fix indentation and remove empty lines
by Felix Singer (Code Review) 12 Jul '21

12 Jul '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56211 to look at the new patch set (#2). Change subject: mb/intel/kblrvp/variants: Fix indentation and remove empty lines ...................................................................... mb/intel/kblrvp/variants: Fix indentation and remove empty lines Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb 2 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/56211/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5e0992494949bcb2fbda1361e0118c087a437a Gerrit-Change-Number: 56211 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021