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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: drivers/pc80/rtc: Make use of alt-century byte configurable
......................................................................
drivers/pc80/rtc: Make use of alt-century byte configurable
This legacy alt-century byte sits amidst CMOS and conflicts many option
tables. It usually has no meaning to the hardware and needs to be main-
tained manually. Let's disable its usage by default if the CMOS option
table is enabled.
Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/drivers/pc80/rtc/Kconfig
M src/drivers/pc80/rtc/mc146818rtc.c
2 files changed, 19 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/56214/2
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Change subject: Documentation: Add proposal to allow enabling serial console with a flag
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File Documentation/technotes/2021-05-selectable-serial-console.md:
https://review.coreboot.org/c/coreboot/+/54385/comment/e18cb3c1_0a596582
PS6, Line 133: reason
nit: plural `reasons`
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Change subject: console: Allow configuring log level through CBFS
......................................................................
Patch Set 17: Code-Review+1
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Change subject: lib/Makefile.inc: Remove effect-free line
......................................................................
Patch Set 1: Code-Review+2
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Hello build bot (Jenkins), Greg Edelston, Jakub Czapiga, Paul Menzel, Julius Werner, Angel Pons, Dossym Nurmukhanov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45208
to look at the new patch set (#17).
Change subject: console: Allow configuring log level through CBFS
......................................................................
console: Allow configuring log level through CBFS
Allow configuring loglevel through CBFS in addition to the compile
time default and the (not always available) "CMOS" nvram.
In the first stage (usually bootblock), only the compile time default
is used (no change to previous behavior)
Later stages first look for valid configuration in nvram, then in
CBFS and finally use the compile time default: The first usable value
is chosen.
"Fast" consoles still log at BIOS_DEBUG level or slow console loglevel,
whatever is more verbose.
With this change a single image can be used both for deployment and
testing scenarios with only a dedicated CBFS file modified to toggle
(the typically slow) serial console.
BUG=b:151346403
BRANCH=none
TEST=Taking a Chrome OS config for google/hatch, it behaves as
expected with no entry present and both entry states with negligible
performance loss.
Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M src/console/init.c
M tests/console/Makefile.inc
2 files changed, 19 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45208/17
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Change subject: Documentation: Remove KASAN from the project ideas list
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56179 )
Change subject: include/cpu/x86/msr: fix MCG_CTL_P definition
......................................................................
include/cpu/x86/msr: fix MCG_CTL_P definition
MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of
that MSR contain the number of MCA banks being present on the CPU. At
the moment this definition of MCG_CTL_P is unused.
Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56179
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/include/cpu/x86/msr.h
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
Angel Pons: Looks good to me, approved
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index ac48ca2..748aed5 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -36,7 +36,7 @@
#define SMBASE_RO_MSR 0x98
#define IA32_SMM_MONITOR_VALID (1 << 0)
#define IA32_MCG_CAP 0x179
-#define MCG_CTL_P (1 << 3)
+#define MCG_CTL_P (1 << 8)
#define MCA_BANKS_MASK 0xff
#define IA32_PERF_STATUS 0x198
#define IA32_PERF_CTL 0x199
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Change subject: drivers/pc80/mc146818rtc: Check date and time for sanity
......................................................................
Patch Set 5:
(1 comment)
File src/lib/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/54914/comment/72f3f352_349e0047
PS5, Line 62: bootblcok
um
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