coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: qualcomm/sc7280: gpio: Support eGPIO scheme
by Taniya Das (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, Julius Werner, mturney mturney. Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55078 ) Change subject: qualcomm/sc7280: gpio: Support eGPIO scheme ...................................................................... Patch Set 12: (1 comment) File src/soc/qualcomm/sc7280/sc7280_egpio.c: https://review.coreboot.org/c/coreboot/+/55078/comment/d785f71f_6674f0ec PS3, Line 56: setbits32(&regs->cfg, BIT(EGPIO_CFG_EN)); > Sorry, I still don't understand. […] Hi Julius, Please take a look at the "https://partnerissuetracker.corp.google.com/issues/168749907" buganizer. This has been a request which we are trying to get in coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/55078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c54a14c50fb7b5921d1961d2de83098ed2d4358 Gerrit-Change-Number: 55078 Gerrit-PatchSet: 12 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:32:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Taniya Das <tdas(a)codeaurora.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Paul Menzel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jamie Ryu, Rizwan Qureshi, Sugnan Prabhu S, Meera Ravindranath. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 85: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/27369/comment/26b70955_3fcdd859 PS85, Line 9: Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) : loading mechanism patches the microcode before CPU reset. Please add a reference to the datasheet (name, revision, section). https://review.coreboot.org/c/coreboot/+/27369/comment/f89849fe_651ca7fa PS85, Line 15: chromebooks Chromebooks -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 85 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:29:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbfstool: Remove unused pagesize parameter
by Kyösti Mälkki (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Julius Werner, Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55581 ) Change subject: util/cbfstool: Remove unused pagesize parameter ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib672ba8ed418b1a76e4a48951eabda6923358e7a Gerrit-Change-Number: 55581 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:28:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: UPSTREAM: mb/google/volteer/variants/collis: Fix pen ejection event
by Paul Menzel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Chu, Isaac Lee, Tim Wawrzynczak, Zhuohao Lee. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56331 ) Change subject: UPSTREAM: mb/google/volteer/variants/collis: Fix pen ejection event ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56331/comment/82974e0f_d215b619 PS2, Line 2: FrankChu Frank Chu https://review.coreboot.org/c/coreboot/+/56331/comment/a4cd4261_046dcaaa PS2, Line 7: UPSTREAM: Please remove. https://review.coreboot.org/c/coreboot/+/56331/comment/5af51f99_93135ee9 PS2, Line 13: evtest ,SW_PEN_INSERT Please put the space after the comma. https://review.coreboot.org/c/coreboot/+/56331/comment/f53c3422_06aabd6c PS2, Line 15: FrankChu Frank Chu -- To view, visit https://review.coreboot.org/c/coreboot/+/56331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida5e5b35464471a7896cef392e178a3d2c0ea1aa Gerrit-Change-Number: 56331 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:21:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS
by Paul Menzel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Subrata Banik, Angel Pons, Arthur Heymans, Morgan Jang, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56332 ) Change subject: soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d Gerrit-Change-Number: 56332 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:19:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
by Angel Pons (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56005 ) Change subject: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM ...................................................................... Patch Set 3: (3 comments) File src/soc/intel/common/block/acpi/pep.c: https://review.coreboot.org/c/coreboot/+/56005/comment/dce81902_d8358a49 PS3, Line 32: uint32_t *reg = calloc(LPM_REGISTERS_COUNT, sizeof(uint32_t)); Hmmm, I don't like using dynamically allocating memory when the buffer size is known at compile-time. Given that this is a static function, I would have the array as a local variable in `generate_acpi_power_engine()` and pass it to this function as a parameter. Another option would be to declare the array in this function as static, and return a pointer to it. This would work because static variables in a function persist after the function returns, but I'm not sure how clean it would be. https://review.coreboot.org/c/coreboot/+/56005/comment/090287ac_41ca74f5 PS3, Line 183: LPM_REGISTERS_COUNT * sizeof(uint32_t) I'd really like to avoid open-coding the size of this thing. https://review.coreboot.org/c/coreboot/+/56005/comment/1914a669_4a295979 PS3, Line 197: DSM_UUID(PEP_S0IX_UUID, pep_s0ix, ARRAY_SIZE(pep_s0ix), (void *)reg), > nit: Is there value in exposing this _DSM with 0 supported functions if !SOC_INTEL_COMMON_BLOCK_ACPI […] +1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b Gerrit-Change-Number: 56005 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:18:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/mediatek/mt8195: Remove redundant code
by Rex-BC Chen (Code Review) 15 Jul '21

15 Jul '21

Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56203 ) Change subject: vc/mediatek/mt8195: Remove redundant code ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56203/comment/c916c794_11caae61 PS4, Line 8: > Please elaborate next time. ok, thanks for reviewing. -- To view, visit https://review.coreboot.org/c/coreboot/+/56203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10b2d3c6cb3480f9e3e3232b5ce87ecf7074bbbf Gerrit-Change-Number: 56203 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:16:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel: Add dedicated file to grow Intel CPUIDs
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Mariusz Szafrański, Jonathan Zhang, Johnny Lin, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56333 ) Change subject: cpu/intel: Add dedicated file to grow Intel CPUIDs ...................................................................... cpu/intel: Add dedicated file to grow Intel CPUIDs This patch removes all local `CPUID_` macros from SoC directories and creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC users are expected to add any new CPUID support into cpu_ids.h and include 'cpu/intel/cpu_ids.h' into respective files that look for `CPUID_` macro. Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/intel/haswell/haswell.h A src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/denverton_ns/include/soc/cpu.h M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h M src/soc/intel/xeon_sp/skx/include/soc/cpu.h 6 files changed, 81 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/56333/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 133a129..3197bd8 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -4,33 +4,9 @@ #define _CPU_INTEL_HASWELL_H #include <arch/cpu.h> +#include <cpu/intel/cpu_ids.h> #include <stdint.h> -/* CPU types without stepping */ -#define HASWELL_FAMILY_TRAD 0x306c0 -#define HASWELL_FAMILY_ULT 0x40650 -#define CRYSTALWELL_FAMILY 0x306c0 -#define BROADWELL_FAMILY_ULT 0x306d0 - -/* Haswell CPUIDs */ -#define CPUID_HASWELL_A0 0x306c1 -#define CPUID_HASWELL_B0 0x306c2 -#define CPUID_HASWELL_C0 0x306c3 - -#define CPUID_HASWELL_ULT_B0 0x40650 -#define CPUID_HASWELL_ULT_C0 0x40651 - -/* Crystalwell CPUIDs */ -#define CPUID_CRYSTALWELL_B0 0x40660 -#define CPUID_CRYSTALWELL_C0 0x40661 - -/* Broadwell CPUIDs */ -#define CPUID_BROADWELL_C0 0x40671 - -#define CPUID_BROADWELL_ULT_C0 0x306d2 -#define CPUID_BROADWELL_ULT_D0 0x306d3 -#define CPUID_BROADWELL_ULT_E0 0x306d4 - /* Haswell and Broadwell bus clock is fixed at 100MHz */ #define CPU_BCLK 100 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h new file mode 100644 index 0000000..0433f0c --- /dev/null +++ b/src/include/cpu/intel/cpu_ids.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef CPU_INTEL_CPU_IDS_H +#define CPU_INTEL_CPU_IDS_H + +/* Supported CPUIDs for different Intel CPU */ + +/* CPU types without stepping */ +#define HASWELL_FAMILY_TRAD 0x306c0 +#define HASWELL_FAMILY_ULT 0x40650 +#define CRYSTALWELL_FAMILY 0x306c0 +#define BROADWELL_FAMILY_ULT 0x306d0 + +/* CPUIDs with stepping */ +#define CPUID_HASWELL_A0 0x306c1 +#define CPUID_HASWELL_B0 0x306c2 +#define CPUID_HASWELL_C0 0x306c3 +#define CPUID_HASWELL_ULT_B0 0x40650 +#define CPUID_HASWELL_ULT_C0 0x40651 +#define CPUID_CRYSTALWELL_B0 0x40660 +#define CPUID_CRYSTALWELL_C0 0x40661 +#define CPUID_BROADWELL_C0 0x40671 +#define CPUID_BROADWELL_ULT_C0 0x306d2 +#define CPUID_BROADWELL_ULT_D0 0x306d3 +#define CPUID_BROADWELL_ULT_E0 0x306d4 +#define CPUID_DENVERTON_A0_A1 0x506f0 +#define CPUID_DENVERTON_B0 0x506f1 +#define CPUID_COOPERLAKE_SP_A0 0x5065a +#define CPUID_COOPERLAKE_SP_A1 0x5065b +#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 +#define CPUID_SKYLAKE_SP_B0 0x506f1 +#define CPUID_SKYLAKE_SP_4 0x50654 +#define CPUID_SKYLAKE_C0 0x406e2 +#define CPUID_SKYLAKE_D0 0x406e3 +#define CPUID_SKYLAKE_HQ0 0x506e1 +#define CPUID_SKYLAKE_HR0 0x506e3 +#define CPUID_KABYLAKE_G0 0x406e8 +#define CPUID_KABYLAKE_H0 0x806e9 +#define CPUID_KABYLAKE_Y0 0x806ea +#define CPUID_KABYLAKE_HA0 0x506e8 +#define CPUID_KABYLAKE_HB0 0x906e9 +#define CPUID_CANNONLAKE_A0 0x60660 +#define CPUID_CANNONLAKE_B0 0x60661 +#define CPUID_CANNONLAKE_C0 0x60662 +#define CPUID_CANNONLAKE_D0 0x60663 +#define CPUID_APOLLOLAKE_A0 0x506c8 +#define CPUID_APOLLOLAKE_B0 0x506c9 +#define CPUID_APOLLOLAKE_E0 0x506ca +#define CPUID_GLK_A0 0x706a0 +#define CPUID_GLK_B0 0x706a1 +#define CPUID_GLK_R0 0x706a8 +#define CPUID_WHISKEYLAKE_V0 0x806ec +#define CPUID_WHISKEYLAKE_W0 0x806eb +#define CPUID_COFFEELAKE_U0 0x906ea +#define CPUID_COFFEELAKE_B0 0x906eb +#define CPUID_COFFEELAKE_P0 0x906ec +#define CPUID_COFFEELAKE_R0 0x906ed +#define CPUID_ICELAKE_A0 0x706e0 +#define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE_A0 0x906c0 +#define CPUID_COMETLAKE_U_A0 0xa0660 +#define CPUID_COMETLAKE_U_K0_S0 0xa0661 +#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 +#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 +#define CPUID_TIGERLAKE_A0 0x806c0 +#define CPUID_TIGERLAKE_B0 0x806c1 +#define CPUID_ELKHARTLAKE_A0 0x90660 +#define CPUID_ELKHARTLAKE_B0 0x90661 +#define CPUID_ALDERLAKE_S_A0 0x90670 +#define CPUID_ALDERLAKE_A0 0x906a0 +#define CPUID_ALDERLAKE_A1 0x906a1 +#define CPUID_ALDERLAKE_A2 0x906a2 + +#endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index dd2653b..8a413ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -3,51 +3,10 @@ #ifndef SOC_INTEL_COMMON_BLOCK_MP_INIT_H #define SOC_INTEL_COMMON_BLOCK_MP_INIT_H +#include <cpu/intel/cpu_ids.h> #include <device/device.h> /* Supported CPUIDs for different SOCs */ -#define CPUID_SKYLAKE_C0 0x406e2 -#define CPUID_SKYLAKE_D0 0x406e3 -#define CPUID_SKYLAKE_HQ0 0x506e1 -#define CPUID_SKYLAKE_HR0 0x506e3 -#define CPUID_KABYLAKE_G0 0x406e8 -#define CPUID_KABYLAKE_H0 0x806e9 -#define CPUID_KABYLAKE_Y0 0x806ea -#define CPUID_KABYLAKE_HA0 0x506e8 -#define CPUID_KABYLAKE_HB0 0x906e9 -#define CPUID_CANNONLAKE_A0 0x60660 -#define CPUID_CANNONLAKE_B0 0x60661 -#define CPUID_CANNONLAKE_C0 0x60662 -#define CPUID_CANNONLAKE_D0 0x60663 -#define CPUID_APOLLOLAKE_A0 0x506c8 -#define CPUID_APOLLOLAKE_B0 0x506c9 -#define CPUID_APOLLOLAKE_E0 0x506ca -#define CPUID_GLK_A0 0x706a0 -#define CPUID_GLK_B0 0x706a1 -#define CPUID_GLK_R0 0x706a8 -#define CPUID_WHISKEYLAKE_V0 0x806ec -#define CPUID_WHISKEYLAKE_W0 0x806eb -#define CPUID_COFFEELAKE_U0 0x906ea -#define CPUID_COFFEELAKE_B0 0x906eb -#define CPUID_COFFEELAKE_P0 0x906ec -#define CPUID_COFFEELAKE_R0 0x906ed -#define CPUID_ICELAKE_A0 0x706e0 -#define CPUID_ICELAKE_B0 0x706e1 -#define CPUID_JASPERLAKE_A0 0x906c0 -#define CPUID_COMETLAKE_U_A0 0xa0660 -#define CPUID_COMETLAKE_U_K0_S0 0xa0661 -#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 -#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 -#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 -#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 -#define CPUID_TIGERLAKE_A0 0x806c0 -#define CPUID_TIGERLAKE_B0 0x806c1 -#define CPUID_ELKHARTLAKE_A0 0x90660 -#define CPUID_ELKHARTLAKE_B0 0x90661 -#define CPUID_ALDERLAKE_S_A0 0x90670 -#define CPUID_ALDERLAKE_A0 0x906a0 -#define CPUID_ALDERLAKE_A1 0x906a1 -#define CPUID_ALDERLAKE_A2 0x906a2 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index 0f9d3ace..f4b0d3c 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -3,6 +3,8 @@ #ifndef _CPU_INTEL_DENVERTON_NS_H #define _CPU_INTEL_DENVERTON_NS_H +#include <cpu/intel/cpu_ids.h> + int get_cpu_count(void); #ifndef __ASSEMBLER__ @@ -14,10 +16,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -/* Denverton-NS CPUID */ -#define CPUID_DENVERTON_A0_A1 0x506f0 -#define CPUID_DENVERTON_B0 0x506f1 - #define MSR_CORE_THREAD_COUNT 0x35 #define CORE_BIT_MSK 0x1 #define MCH_BAR_CORE_EXISTS_MASK 0x7164 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 716fe29e..d00c27f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -4,11 +4,9 @@ #define _SOC_CPU_H #include <device/device.h> +#include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h> -#define CPUID_COOPERLAKE_SP_A0 0x5065a -#define CPUID_COOPERLAKE_SP_A1 0x5065b - void cpx_init_cpus(struct device *dev); #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index 433598b..ef712ab 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -4,13 +4,9 @@ #define _SOC_CPU_H_ #include <device/device.h> +#include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h> -/* SKXSP CPUID */ -#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 -#define CPUID_SKYLAKE_SP_B0 0x506f1 -#define CPUID_SKYLAKE_SP_4 0x50654 - /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 -- To view, visit https://review.coreboot.org/c/coreboot/+/56333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Gerrit-Change-Number: 56333 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56332 ) Change subject: soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS ...................................................................... soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS This patch removes leading zero from CPUIDs as below: 0x05065a -> 0x5065a 0x05065b -> 0x5065b Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56332/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 693de8f..716fe29e 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -6,8 +6,8 @@ #include <device/device.h> #include <cpu/x86/msr.h> -#define CPUID_COOPERLAKE_SP_A0 0x05065a -#define CPUID_COOPERLAKE_SP_A1 0x05065b +#define CPUID_COOPERLAKE_SP_A0 0x5065a +#define CPUID_COOPERLAKE_SP_A1 0x5065b void cpx_init_cpus(struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/56332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d Gerrit-Change-Number: 56332 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: console: Handle verstage as "first non-bootblock stage"
by Nico Huber (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Julius Werner. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56210 ) Change subject: console: Handle verstage as "first non-bootblock stage" ...................................................................... Patch Set 1: (1 comment) File src/console/init.c: https://review.coreboot.org/c/coreboot/+/56210/comment/ff21e811_82d83f95 PS1, Line 15: #endif > For one, some stages are _pretty_ packed, e.g. verstage on google/veyron. Especially with the follow-on that takes a couple more bytes to add CBFS support, verstage is overflowing there, so cutting down on that is worthwhile. Well this patch would only decrease verstage size if the bootblock console is disabled and get_uint_option() isn't used otherwise. That's rather subtle. > Okay, I think we're all confused about what we're talking about now. ^^ What I mean is using ENV_INITIAL_STAGE instead of the the FIRST_CONSOLE macro that gets defined here. So the code in init_log_level() should just read: > > console_loglevel = get_console_loglevel(); > > if (!ENV_INITIAL_STAGE) > console_loglevel = get_uint_option("debug_level", console_loglevel); > > (and then the stuff Patrick adds in the next patch would also fall under that). That way we don't need an extra FIRST_CONSOLE macro and all the vboot stage ordering stuff has already been taken care of correctly in the definition > of ENV_INITIAL_STAGE. That's what I already understood so far. > > If the question is why we need any check at all and can't just call get_uint_option() in every stage... I don't know, I'm not super familiar with how CMOS stuff works on x86. Are there any platforms where accessing CMOS requires any sort of platform-specific setup beforehand? For CBFS that is definitely the case, so at least for CBFS we need to prevent accesses in the first stage. For CMOS, if you're sure that no point to call it would be too early, I guess it doesn't matter. There are no known special requirements. And if there were, they should be handled behind the API and not here, right? It's also not the CBFS-API users that check ENV_INITIAL_STAGE. The whole point of FIRST_CONSOLE really was just to keep complexity low for the very first effective print (no matter in what stage the console starts). So that can't be achieved with ENV_INITIAL_STAGE. I think we should either go with Patrick's patch or just always call get_uint_option(). -- To view, visit https://review.coreboot.org/c/coreboot/+/56210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I494a33483e306a049aa0c8137a118644fc28177e Gerrit-Change-Number: 56210 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 08:49:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit July 2021