coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B
by Frank Wu (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56328 ) Change subject: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56328/comment/a3b452f1_baf3b9ea PS1, Line 7: zork/vilboz > I believe, zork/var/vilboz is commonly used. Done https://review.coreboot.org/c/coreboot/+/56328/comment/4c2330bd_3414ff68 PS1, Line 7: for vilboz > Redundant, as already in prefix. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Gerrit-Change-Number: 56328 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:41:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B
by Frank Wu (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Wu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56328 to look at the new patch set (#2). Change subject: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B ...................................................................... mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B Add new ram_id:1000 for memory part MT40A1G16RC-062E:B. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:193732051 TEST=build coreboot and boot from the DUT with memory MT40A1G16RC-062E:B Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 --- M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56328/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Gerrit-Change-Number: 56328 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Meera Ravindranath (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jamie Ryu, Sugnan Prabhu S, Meera Ravindranath. Meera Ravindranath has uploaded a new patch set (#84) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC (BUC) PCR register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc M src/soc/intel/common/basecode/Kconfig A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c 8 files changed, 668 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/84 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 84 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: UPSTREAM: mb/google/dedede/var/pirika: Add USB2 PHY parameters
by Paul Menzel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Alex1 Kao, Kirk Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56327 ) Change subject: UPSTREAM: mb/google/dedede/var/pirika: Add USB2 PHY parameters ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56327/comment/6e56cb8b_0ff8c530 PS1, Line 7: UPSTREAM: This is a Chromium repository tag to my knowledge. Please remove. https://review.coreboot.org/c/coreboot/+/56327/comment/2a98df05_426487ec PS1, Line 9: This change adds fine-tuned USB2 PHY parameters for pirika. Please add, where you got these from. -- To view, visit https://review.coreboot.org/c/coreboot/+/56327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf9fb41cd0ae40728e4ec5bd72a15ec3c45c963b Gerrit-Change-Number: 56327 Gerrit-PatchSet: 1 Gerrit-Owner: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Attention: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:31:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Furquan Shaikh (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Martin Roth, Michał Żygowski, Marshall Dawson, Subrata Banik, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/f1d630d2_3457eb97 PS3, Line 14: looks_like_fsp_header > irrespective of you are considering this new API or not, inclusion of MultiSi API into your EDK2 header actually claim the FSP header size == 76 as align with FSP 2.2 I think that is fine. When the particular FSP version is defined, it captures the size of the header at that point. So, coreboot as consumer needs to ensure that we have at least that many bytes to consume. If it is greater, we don't really need to care about the additional bytes. The additional bytes will have to be just considered invalid. Also, coreboot shouldn't really look at those bytes anyways since the reported version doesn't know how to use those bytes. > If we had compile type option then yes, we can say that based on HeaderRevision (PcdFspHeaderRevision) < 5, during compilation time EDK2 would drop inclusion of FspMultiPhaseSiInitEntryOffset hence the output FSP header would be 76-4 = 72. But unfortunately its static hence this kind of mismatch issue i was referring. We don't really need any compile time difference. Like I explained above, the additional bytes in the header are considered invalid by the consumer and will be ignored. > patch looks good, but only consideration point imo is that, now its easy that one could add more APIs (using EDK2 override in platform code) and can grow the FSP header beyond what spec had mentioned and bootloader won't have any way to catch that as it would always pass the min size limit. If more fields are added to the header but the version is still older, bootloader should conform to the reported version and ignore rest of the fields as invalid. If the bytes are unused, do we care about what is in those fields at all? -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:31:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork/vilboz: Add new memory MT40A1G16RC-062E:B for vilboz
by Paul Menzel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56328 ) Change subject: mb/google/zork/vilboz: Add new memory MT40A1G16RC-062E:B for vilboz ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56328/comment/7b49221d_666a525c PS1, Line 7: zork/vilboz I believe, zork/var/vilboz is commonly used. https://review.coreboot.org/c/coreboot/+/56328/comment/6b27a1f0_cb0c478c PS1, Line 7: for vilboz Redundant, as already in prefix. -- To view, visit https://review.coreboot.org/c/coreboot/+/56328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Gerrit-Change-Number: 56328 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:30:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: x86/smp/spinlock: Disable thread coop when taking spinlock
by Furquan Shaikh (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Raul Rangel, Julius Werner. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56320 ) Change subject: x86/smp/spinlock: Disable thread coop when taking spinlock ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/include/arch/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/56320/comment/d44da6e7_8d5fb829 PS1, Line 61: lock->coop = thread_coop_enabled(); > These spinlocks are primarily for the actual SMP in ramstage, not for the thread mechanism...However, I think(?) the non-boot CPUs actually can't participate in the thread mechanism anyway. I just see thread_init_non_bsp_cpu() set their cpu_info->thread pointer to NULL and I don't think it ever changes from that. So there's no real point in storing coop status for them. That is correct. The thread mechanism is implemented for the BSP-only. All other non-BSP CPUs have their thread pointer set to NULL and it stays that way forever. The thread mechanism is for co-operative threads on the BSP where the main thread typically has a lot of busy loops and so the tasks can be multiplexed into multiple threads. In fact, the expectation is that the caller ensures the threads do not use any shared resources (which can be the UART console in this case ;)). > Maybe the best option would be to just make thread_cooperate() and thread_prevent_coop() work like a semaphore instead of a boolean value? That suggestion makes sense to me. It will ensure that the thread does not yield if it hasn't already prevented coop and will be restored back to the same state after the lock is released. -- To view, visit https://review.coreboot.org/c/coreboot/+/56320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b929070b7f175965d4f37be693462fef26be052 Gerrit-Change-Number: 56320 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:25:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork/vilboz: Add new memory MT40A1G16RC-062E:B for vilboz
by Frank Wu (Code Review) 15 Jul '21

15 Jul '21

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56328 ) Change subject: mb/google/zork/vilboz: Add new memory MT40A1G16RC-062E:B for vilboz ...................................................................... mb/google/zork/vilboz: Add new memory MT40A1G16RC-062E:B for vilboz Add new ram_id:1000 for memory part MT40A1G16RC-062E:B. Command to generate files: go build gen_part_id.go local variant=vilboz ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt BUG=b:193732051 TEST=build coreboot and boot from the DUT with memory MT40A1G16RC-062E:B Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 --- M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56328/1 diff --git a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc index c7890d0..e4daa51 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc @@ -10,3 +10,4 @@ SPD_SOURCES += ddr4-spd-7.hex # ID = 5(0b0101) Parts = K4AAG165WA-BCWE SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NDMR-XNC +SPD_SOURCES += ddr4-spd-9.hex # ID = 8(0b1000) Parts = MT40A1G16RC-062E:B diff --git a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt index 8afd956..5a71ea9 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt @@ -5,3 +5,4 @@ K4AAG165WA-BCWE 5 (0101) MT40A1G16KD-062E:E 6 (0110) H5ANAG6NDMR-XNC 7 (0111) +MT40A1G16RC-062E:B 8 (1000) diff --git a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt index 2b8d6df..8ca7407 100644 --- a/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt @@ -13,3 +13,4 @@ K4AAG165WA-BCWE, 5 MT40A1G16KD-062E:E, 6 H5ANAG6NDMR-XNC, 7 +MT40A1G16RC-062E:B, 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Gerrit-Change-Number: 56328 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/starlabs: Add Star Labs ITE 5570E support
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Sean Rhodes, Paul Menzel, Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55263 ) Change subject: ec/starlabs: Add Star Labs ITE 5570E support ...................................................................... Patch Set 20: (1 comment) File src/ec/starlabs/it5570/Kconfig: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124273): https://review.coreboot.org/c/coreboot/+/55263/comment/6a6f67a2_071a7df3 PS20, Line 15: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 20 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 06:50:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: spi: Limit the SPI NOR size
by Sajida Bhanu (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Ravi kumar, Paul Menzel, Julius Werner. Sajida Bhanu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55376 ) Change subject: spi: Limit the SPI NOR size ...................................................................... Patch Set 11: (1 comment) Patchset: PS1: > Yes, this patch as you uploaded here is unacceptable. […] Sure thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/55376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f3f402b383bbad303f26c31d3d973c5f20d172 Gerrit-Change-Number: 55376 Gerrit-PatchSet: 11 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 06:34:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sajida Bhanu <sbhanu(a)codeaurora.org> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021