coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/alderlake: Configure the SKU specific parameters for VR dom...
by V Sowmya (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56325 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Configure the SKU specific parameters for VR domains ...................................................................... soc/intel/alderlake: Configure the SKU specific parameters for VR domains This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/include/soc/vr_config.h A src/soc/intel/alderlake/vr_config.c 5 files changed, 215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/56325/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Gerrit-Change-Number: 56325 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
by V Sowmya (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Vinay Kumar, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili. Hello build bot (Jenkins), Kedar J. Karanje, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Vinay Kumar, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56176 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL ...................................................................... soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU specific values from the FSP default value 160. * ADL-P 682(45W) = 137. * ADL-P 482(28W) = 128. * ADL-P 282(15W) = 128. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/56176/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Gerrit-Change-Number: 56176 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
by Zhuohao Lee (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Chu, Isaac Lee, Tim Wawrzynczak, Nick Vaccaro. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56302 ) Change subject: mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9 Gerrit-Change-Number: 56302 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <ansontseng(a)google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 03:21:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure the SKU specific parameters for VR dom...
by V Sowmya (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: V Sowmya, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56325 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Configure the SKU specific parameters for VR domains ...................................................................... soc/intel/alderlake: Configure the SKU specific parameters for VR domains This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/include/soc/vr_config.h A src/soc/intel/alderlake/vr_config.c 5 files changed, 215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/56325/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Gerrit-Change-Number: 56325 Gerrit-PatchSet: 3 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Configure the SKU specific parameters for VR dom...
by V Sowmya (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56325 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Configure the SKU specific parameters for VR domains ...................................................................... soc/intel/alderlake: Configure the SKU specific parameters for VR domains This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+---------+-------+-------+---------+-----------+---------+ | SKU | Setting | AC LL | DC LL | ICC MAX |TDC Current| TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+---------+-------+-------+---------+-----------+---------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +---------+-------+-------+---------+-----------+---------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+---------+-------+-------+---------+-----------+---------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +---------+-------+-------+---------+-----------+---------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +----------------+-------+-------+-------+---------+-----------+---------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +---------+-------+-------+---------+-----------+---------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+---------+-------+-------+---------+-----------+---------+ Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/include/soc/vr_config.h A src/soc/intel/alderlake/vr_config.c 5 files changed, 215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/56325/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Gerrit-Change-Number: 56325 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
by Furquan Shaikh (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Vinay Kumar, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56176 ) Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56176/comment/725a3bbf_9ff09440 PS4, Line 294: PCI_DEVICE_ID_INTEL_ADL_P_ID_3 Why are we checking only PCI_DEVICE_ID_INTEL_ADL_P_ID_3/5/7? What about 1/2/4/6/8/9? And what about M? -- To view, visit https://review.coreboot.org/c/coreboot/+/56176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Gerrit-Change-Number: 56176 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 03:01:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure the SKU specific parameters for VR dom...
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56325 ) Change subject: soc/intel/alderlake: Configure the SKU specific parameters for VR domains ...................................................................... Patch Set 1: (5 comments) File src/soc/intel/alderlake/include/soc/vr_config.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124265): https://review.coreboot.org/c/coreboot/+/56325/comment/778e8c8f_55b5583f PS1, Line 79: void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, need consistent spacing around '*' (ctx:WxV) File src/soc/intel/alderlake/vr_config.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124265): https://review.coreboot.org/c/coreboot/+/56325/comment/252b10ea_5d142197 PS1, Line 20: * | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124265): https://review.coreboot.org/c/coreboot/+/56325/comment/20331f13_e265d7c0 PS1, Line 24: * | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124265): https://review.coreboot.org/c/coreboot/+/56325/comment/4716cb2e_bc534a17 PS1, Line 28: * | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124265): https://review.coreboot.org/c/coreboot/+/56325/comment/02f23438_4541a210 PS1, Line 105: else { else should follow close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/56325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Gerrit-Change-Number: 56325 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 02:59:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure the SKU specific parameters for VR dom...
by V Sowmya (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56325 ) Change subject: soc/intel/alderlake: Configure the SKU specific parameters for VR domains ...................................................................... soc/intel/alderlake: Configure the SKU specific parameters for VR domains This patch configures the SKU specific power delivery parameters for the VR domains. +----------------+-----------+-------+-------+---------+-------------+----------+ | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | +----------------+-----------+-------+-------+---------+-------------+----------+ | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-----------+-------+-------+---------+-------------+----------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +----------------+-----------+-------+-------+---------+-------------+----------+ | ADL-P 482(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-----------+-------+-------+---------+-------------+----------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +----------------+-----------+-------+-------+---------+-------------+----------+ | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-----------+-------+-------+---------+-------------+----------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +----------------+-----------+-------+-------+---------+-------------+----------+ Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/include/soc/vr_config.h A src/soc/intel/alderlake/vr_config.c 5 files changed, 215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/56325/1 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index bb57560..783a445 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += reset.c ramstage-y += soundwire.c ramstage-y += systemagent.c +ramstage-y += vr_config.c ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 077a58d..248eedf 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -15,6 +15,7 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/usb.h> +#include <soc/vr_config.h> #include <stdint.h> /* Types of different SKUs */ @@ -391,6 +392,11 @@ /* External Icc Max for VnnSx rail in mA */ int vnn_icc_max_ma; } ext_fivr_settings; + + /* VrConfig Settings. + * 0 = VR_DOMAIN_IA Core 1 = VR_DOMAIN_GT. + */ + struct vr_config domain_vr_config[NUM_VR_DOMAINS]; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 7ba8abe..fe897a2 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -608,6 +608,11 @@ * Values are in 1/4 Amp increments and range is 0-512. */ s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax(); + + /* VrConfig Settings for IA and GT domains */ + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); + } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/alderlake/include/soc/vr_config.h b/src/soc/intel/alderlake/include/soc/vr_config.h new file mode 100644 index 0000000..3976037 --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/vr_config.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* VR Settings for each domain */ + +#ifndef _SOC_VR_CONFIG_H_ +#define _SOC_VR_CONFIG_H_ + +#include <fsp/api.h> + +struct vr_config { + + /* The below settings will take effect when this is set to 1 for that domain. */ + uint8_t vr_config_enable; + + /* AC and DC Loadline. + * They are in 1/100 mOhms (ie. 1250 = 12.50 mOhms) and range is 0-6249. + */ + uint16_t ac_loadline; + uint16_t dc_loadline; + + /* VR Icc Max limit. + * Range is from 0-255A in 1/4 A units (400 = 100A). + */ + uint16_t icc_max; + + /* Thermal Design Current (TDC) enable/disable. + * Time window and current limit will take effect when this is set to 1. + */ + uint8_t tdc_enable; + + /* Thermal Design Current time window. + * Defined in milli seconds and range 1ms to 448s. + */ + uint32_t tdc_timewindow; + + /* Thermal Design Current current limit. + * Defined in 1/8A units and range is 0-4095. 1000 = 125A. + */ + uint16_t tdc_currentlimit; +}; + +#define VR_CFG_AMP(i) (uint16_t)((i) * 4) +#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) +#define VR_CFG_TDC_AMP(i) (uint16_t)((i) * 8) + +/* VrConfig Settings for 4 domains + * 0 = IA core, 1 = GT + */ +enum vr_domain { + VR_DOMAIN_IA, + VR_DOMAIN_GT, + NUM_VR_DOMAINS +}; + +#define VR_CFG_ALL_DOMAINS_LOADLINE(ia, gt) \ + { \ + [VR_DOMAIN_IA] = VR_CFG_MOHMS(ia), \ + [VR_DOMAIN_GT] = VR_CFG_MOHMS(gt), \ + } + +#define VR_CFG_ALL_DOMAINS_ICC(ia, gt) \ + { \ + [VR_DOMAIN_IA] = VR_CFG_AMP(ia), \ + [VR_DOMAIN_GT] = VR_CFG_AMP(gt), \ + } + +#define VR_CFG_ALL_DOMAINS_TDC(ia, gt) \ + { \ + [VR_DOMAIN_IA] = ia, \ + [VR_DOMAIN_GT] = gt, \ + } + +#define VR_CFG_ALL_DOMAINS_TDC_CURRENT(ia, gt) \ + { \ + [VR_DOMAIN_IA] = VR_CFG_TDC_AMP(ia), \ + [VR_DOMAIN_GT] = VR_CFG_TDC_AMP(gt), \ + } + +void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, + int domain, const struct vr_config *cfg); +#endif diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c new file mode 100644 index 0000000..7a82e63 --- /dev/null +++ b/src/soc/intel/alderlake/vr_config.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <fsp/api.h> +#include <soc/ramstage.h> +#include <soc/vr_config.h> +#include <console/console.h> +#include <intelblocks/cpulib.h> + +/* + * VR Configurations for IA and GT domains for ADL-P SKU's. + * + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | + * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 109 | 40 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + */ + +struct vr_lookup { + uint16_t mchid; + uint32_t conf[NUM_VR_DOMAINS]; +}; + +static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain, + const uint16_t mch_id) +{ + for (size_t i = 0; i < tbl_entries; i++) { + if (tbl[i].mchid != mch_id) + continue; + return tbl[i].conf[domain]; + } + + printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); + return 0; +} + +static const struct vr_lookup vr_config_ll[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, +}; + +static const struct vr_lookup vr_config_icc[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_ICC(109, 50) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, +}; + +static const struct vr_lookup vr_config_tdc_enable[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC(1, 1) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC(1, 1) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC(1, 1) }, +}; + +static const struct vr_lookup vr_config_tdc_timewindow[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, +}; + +static const struct vr_lookup vr_config_tdc_currentlimit[] = { + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, +}; + +void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, + int domain, const struct vr_config *chip_cfg) +{ + const struct vr_config *cfg; + static uint16_t mch_id = 0; + + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + } + + if (domain < 0 || domain >= NUM_VR_DOMAINS) + return; + + /* Use device tree override if requested */ + if (chip_cfg->vr_config_enable) { + cfg = chip_cfg; + + s_cfg->AcLoadline[domain] = cfg->ac_loadline; + s_cfg->DcLoadline[domain] = cfg->dc_loadline; + s_cfg->IccMax[domain] = cfg->icc_max; + s_cfg->TdcEnable[domain] = cfg->tdc_enable; + s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; + s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; + } + else { + s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), + domain, mch_id); + s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), + domain, mch_id); + s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc), + domain, mch_id); + s_cfg->TdcEnable[domain] = load_table(vr_config_tdc_enable, + ARRAY_SIZE(vr_config_tdc_enable), + domain, mch_id); + s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow, + ARRAY_SIZE(vr_config_tdc_timewindow), + domain, mch_id); + s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, + ARRAY_SIZE(vr_config_tdc_currentlimit), + domain, mch_id); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Gerrit-Change-Number: 56325 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
by V Sowmya (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Kedar J. Karanje, Furquan Shaikh, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Vinay Kumar, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili. Hello build bot (Jenkins), Kedar J. Karanje, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Vinay Kumar, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56176 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL ...................................................................... soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU specific values from the FSP default value 160. * ADL-P 682(45W) = 137. * ADL-P 482(28W) = 128. * ADL-P 282(15W) = 128. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/56176/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Gerrit-Change-Number: 56176 Gerrit-PatchSet: 4 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
by Ken Lu (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Chu, Isaac Lee, Tim Wawrzynczak, Zhuohao Lee. Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56302 ) Change subject: mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17 ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56302/comment/b090bf79_db04444f PS1, Line 11: none > Create a bug for this. I think the FAFT test should catch this problem. Done https://review.coreboot.org/c/coreboot/+/56302/comment/caad08da_c22cc6d4 PS1, Line 12: none > firmware-volteer-13672. […] Done https://review.coreboot.org/c/coreboot/+/56302/comment/adda27f9_cd7d7ea2 PS1, Line 13: none > It shouldn't be none. You need to make sure the pin is working correctly. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9 Gerrit-Change-Number: 56302 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <ansontseng(a)google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 02:51:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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