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Change subject: mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
......................................................................
mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
Redefine GPIO_EC_IN_RW to GPP_F17
BUG=b:193091165
BRANCH=firmware-volteer-13672.B
TEST=verify FAFT firmware_DevMode Pass
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9
---
M src/mainboard/google/volteer/variants/collis/include/variant/gpio.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/56302/4
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
......................................................................
mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
Redefine GPIO_EC_IN_RW to GPP_F17
BUG=b:193091165
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Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9
---
M src/mainboard/google/volteer/variants/collis/include/variant/gpio.h
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/56302/3
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
......................................................................
mb/google/volteer/variants/collis: Redefine GPIO_EC_IN_RW to GPP_F17
Redefine GPIO_EC_IN_RW to GPP_F17
BUG=193091165
BRANCH=none
TEST=none
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I24f4803dc99ef3fc78852241f3a9e86ec70293d9
---
M src/mainboard/google/volteer/variants/collis/include/variant/gpio.h
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/56302/2
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V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56176 )
Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56176/comment/a8fd690a_5a050a0d
PS1, Line 9: VccIn Aux Imon IccMax for ADL to 128
> How is this value determined? Is this dependent on mainboard design?
This is SOC SKU specific value and updated the commit with this info.
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Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56176/comment/699a7aee_e3a0d772
PS1, Line 537: 128
> Is this board-design specific, or common for all ADL boards?
@Tim, This is SOC SKU dependent and modified the code to update it based on SOC SKU.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56318 )
Change subject: lib/thread: Verify threads are initialized before yielding
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/common/block/apob/apob_cache.c:
https://review.coreboot.org/c/coreboot/+/56232/comment/d94c33f8_35a0bf7e
PS6, Line 79: struct apob_thread_context {
Should be static.
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