coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
by Julius Werner (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56232 ) Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV ...................................................................... Patch Set 6: (2 comments) File src/soc/amd/common/block/apob/apob_cache.c: https://review.coreboot.org/c/coreboot/+/56232/comment/0156924a_b094ee6c PS6, Line 71: if (fmap_locate_area(DEFAULT_MRC_CACHE, r) < 0) { off-topic, but I'd really advise against juggling raw regions like this. We have fmap_locate_area_as_rdev() to do this all in one go. https://review.coreboot.org/c/coreboot/+/56232/comment/acc7bf42_2f788fff PS6, Line 135: if (wait_for_thread(&global_apob_thread.handle) == CB_SUCCESS) { I think this should be guarded by COOP_MULTITASKING, it looks weird if you just rely on this returning an error if you never started the thread. -- To view, visit https://review.coreboot.org/c/coreboot/+/56232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 Gerrit-Change-Number: 56232 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jul 2021 01:47:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/thread: Add thread_handle
by Julius Werner (Code Review) 15 Jul '21

15 Jul '21

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Yield after completing transaction
by Julius Werner (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56321 ) Change subject: soc/amd/common/block/lpc/spi_dma: Yield after completing transaction ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/56321/comment/b42d9cce_1d8ab697 PS1, Line 187: udelay(0); I think you should use thread_yield_microseconds(0) instead of udelay(0) if you want to just explicitly yield to coop threads. That way the code itself explains what that's for and you don't need a comment to explain it. (We could also make a thread_yield() as an argument-less shortcut for thread_yield_microseconds(0) if that becomes a commonly needed thing.) -- To view, visit https://review.coreboot.org/c/coreboot/+/56321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0 Gerrit-Change-Number: 56321 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jul 2021 01:07:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/thread: Add mutex
by Julius Werner (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Raul Rangel, Eric Peers, Felix Held. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56230 ) Change subject: lib/thread: Add mutex ...................................................................... Patch Set 5: (5 comments) File src/include/thread.h: https://review.coreboot.org/c/coreboot/+/56230/comment/490e3269_f87728e4 PS5, Line 88: mutex_lock nit: I think it's better to keep everything here prefixed thread_ (e.g. make it thread_mutex_lock() or thread_lock()). File src/lib/thread.c: https://review.coreboot.org/c/coreboot/+/56230/comment/771c1007_ec2474fc PS2, Line 406: thread_yield_microseconds(10); > I had that thought, but wanted to avoid adding a return value to this method. I don't think this function should return in that case, at least. Deadlock is a programming error and it's not safe to just continue execution while ignoring the lock. If anything, you could make it die() after a certain timeout, but it would have to be really long (like 20-30 seconds maybe) to make sure you can't hit it accidentally in cases where people have a lot of slow debug stuff enabled. I'd say a lot of thing in firmware can hang when you write them wrong and firmware engineers are used to debugging that. ;) I don't think we need to add extra monitoring here until it turns out to be a real problem. File src/lib/thread.c: https://review.coreboot.org/c/coreboot/+/56230/comment/2271c9d2_2c97fa8f PS5, Line 391: thread_yield_microseconds(0); Should assert that this didn't fail (e.g. because can_yield is 0, because then you'll wait forever). https://review.coreboot.org/c/coreboot/+/56230/comment/fe66de0c_e4fe10a6 PS5, Line 392: 1 Please only use `true` and `false` with bools, and only numbers with integers. https://review.coreboot.org/c/coreboot/+/56230/comment/4a468bc4_ec3455eb PS5, Line 394: printk(BIOS_DEBUG, " took %lu us to acquire mutex\n", stopwatch_duration_usecs(&sw)); I doubt this is gonna be very useful, since there's 0 context on what thread is waiting on what mutex here. If you want to keep it, maybe make it BIOS_SPEW? (Also, I'm unclear why this starts with a space. Is it supposed to be a direct continuation of another message? Which one?) -- To view, visit https://review.coreboot.org/c/coreboot/+/56230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff Gerrit-Change-Number: 56230 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jul 2021 01:05:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Eric Peers <epeers(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/thread: Add thread_coop_enabled
by Julius Werner (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Raul Rangel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56319 ) Change subject: lib/thread: Add thread_coop_enabled ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: LGTM but I don't think you'll actually need it (see next patch). File src/lib/thread.c: https://review.coreboot.org/c/coreboot/+/56319/comment/36e03d21_3f2a79a5 PS1, Line 371: bool nit: technically `int`, so I'd say either change the thread struct or use 0 and 1 here. -- To view, visit https://review.coreboot.org/c/coreboot/+/56319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90060e21f127fb725f126163aa5b2be6b9d1d117 Gerrit-Change-Number: 56319 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 00:41:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: x86/smp/spinlock: Disable thread coop when taking spinlock
by Julius Werner (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Raul Rangel, Furquan Shaikh. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56320 ) Change subject: x86/smp/spinlock: Disable thread coop when taking spinlock ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/include/arch/smp/spinlock.h: https://review.coreboot.org/c/coreboot/+/56320/comment/a25c6b01_f68618a9 PS1, Line 61: lock->coop = thread_coop_enabled(); I don't think this works, although I'm not very familiar with the x86 SMP stuff. Hopefully +Furquan understands these things better. These spinlocks are primarily for the actual SMP in ramstage, not for the thread mechanism. So you may have two actual physical CPUs spinning on this lock at the same time (while a third one is holding it), and then they'll keep overwriting each other here if you just store this value in the lock struct. If you want a per-CPU copy you'll actually have to put it in the cpu_info or thread structures. However, I think(?) the non-boot CPUs actually can't participate in the thread mechanism anyway. I just see thread_init_non_bsp_cpu() set their cpu_info->thread pointer to NULL and I don't think it ever changes from that. So there's no real point in storing coop status for them. Maybe the best option would be to just make thread_cooperate() and thread_prevent_coop() work like a semaphore instead of a boolean value? I could see that being useful in other cases as well. The fundamental problem here is just that you're calling code that wants to establish a critical section from code that may already be in a critical section -- that situation can happen in all sorts of places and would probably come up again if we start using this API more. If you just make them reference count how many critical sections deep they are, they can take care of this problem themselves (and the non-boot-CPUs would just ignore all those thread_prevent_coop() and thread_cooperate() calls, because their current_thread() is NULL). -- To view, visit https://review.coreboot.org/c/coreboot/+/56320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b929070b7f175965d4f37be693462fef26be052 Gerrit-Change-Number: 56320 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 00:40:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: move check_mca prototype to soc/amd/common/blocks/include
by 9elements QA (Code Review) 15 Jul '21

15 Jul '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56279 ) Change subject: soc/amd: move check_mca prototype to soc/amd/common/blocks/include ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 12 / 1 / 13 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/68012 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/68011 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/68010 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/68009 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/68008 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/68007 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/68006 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/68005 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/68004 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/68003 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/68002 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/68001 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/68000 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/56279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia489dbfba59c334cf29f96a4000cef73b9b797d4 Gerrit-Change-Number: 56279 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 00:03:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/mca: add missing types.h include
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56282 ) Change subject: soc/amd/picasso/mca: add missing types.h include ...................................................................... soc/amd/picasso/mca: add missing types.h include Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56282 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/mca.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 97f5d0b..074f313 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -9,6 +9,7 @@ #include <console/console.h> #include <arch/bert_storage.h> #include <cper.h> +#include <types.h> /* MISC4 is the last used register in the MCAX banks of Picasso */ #define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/56282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Gerrit-Change-Number: 56282 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd: factor out check_mca to common code
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56281 ) Change subject: soc/amd: factor out check_mca to common code ...................................................................... soc/amd: factor out check_mca to common code Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/mca.c M src/soc/amd/common/block/cpu/Kconfig A src/soc/amd/common/block/cpu/mca/Makefile.inc A src/soc/amd/common/block/cpu/mca/mca_common.c M src/soc/amd/common/block/include/amdblocks/mca.h M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/mca.c 10 files changed, 40 insertions(+), 28 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 8f93512..71cca6a 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c index a8d9702..68fae29 100644 --- a/src/soc/amd/cezanne/mca.c +++ b/src/soc/amd/cezanne/mca.c @@ -1,18 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> -#include <cpu/x86/msr.h> -static void mca_check_all_banks(void) +void mca_check_all_banks(void) { /* TODO: Implement MCAX register checking and BERT table generation. */ } - -/* Check the Machine Check Architecture Extension registers */ -void check_mca(void) -{ - mca_check_all_banks(); - /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are - aliases, we can use either set of registers. */ - mca_clear_status(); -} diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 1437326..79e011f 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -26,6 +26,26 @@ endif # SOC_AMD_COMMON_BLOCK_NONCAR +config SOC_AMD_COMMON_BLOCK_MCA_COMMON + bool + help + Add common machine check architecture support. Do not select this + in the SoC's Kconfig; select either SOC_AMD_COMMON_BLOCK_MCA or + SOC_AMD_COMMON_BLOCK_MCAX which will select this one. + +config SOC_AMD_COMMON_BLOCK_MCA + bool + select SOC_AMD_COMMON_BLOCK_MCA_COMMON + help + Add IA32 machine check architecture (MCA) support for pre-Zen CPUs. + +config SOC_AMD_COMMON_BLOCK_MCAX + bool + select SOC_AMD_COMMON_BLOCK_MCA_COMMON + help + Add extended machine check architecture (MCAX) support for AMD family + 17h, 19h and possibly newer CPUs. + config SOC_AMD_COMMON_BLOCK_SMM bool help diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.inc b/src/soc/amd/common/block/cpu/mca/Makefile.inc new file mode 100644 index 0000000..0aa47e1 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON) += mca_common.c diff --git a/src/soc/amd/common/block/cpu/mca/mca_common.c b/src/soc/amd/common/block/cpu/mca/mca_common.c new file mode 100644 index 0000000..0a37508 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mca_common.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <cpu/x86/msr.h> + +void check_mca(void) +{ + mca_check_all_banks(); + /* mca_clear_status uses the MCA registers which can be used in both the MCA and MCAX + case */ + mca_clear_status(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/mca.h b/src/soc/amd/common/block/include/amdblocks/mca.h index 9ea29e8..16b016b 100644 --- a/src/soc/amd/common/block/include/amdblocks/mca.h +++ b/src/soc/amd/common/block/include/amdblocks/mca.h @@ -4,5 +4,6 @@ #define AMD_BLOCK_MCA_H void check_mca(void); +void mca_check_all_banks(void); #endif /* AMD_BLOCK_MCA_H */ diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 42c3bfc..88bff50 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -41,6 +41,7 @@ select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 24a921a..97f5d0b 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -192,7 +192,7 @@ printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } -static void mca_check_all_banks(void) +void mca_check_all_banks(void) { struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); @@ -214,12 +214,3 @@ } } } - -/* Check the Machine Check Architecture Extension registers */ -void check_mca(void) -{ - mca_check_all_banks(); - /* mca_clear_status uses the MCA registers and not the MCAX ones. Since they are - aliases, we can use either set of registers. */ - mca_clear_status(); -} diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 821d1ee..e799ea0 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -33,6 +33,7 @@ select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_MCA select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PM diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index b3e6682..cf3f3ac 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -179,7 +179,7 @@ printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } -static void mca_check_all_banks(void) +void mca_check_all_banks(void) { struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); @@ -201,9 +201,3 @@ } } } - -void check_mca(void) -{ - mca_check_all_banks(); - mca_clear_status(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/56281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Gerrit-Change-Number: 56281 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: thread: Add missing static inline
by Julius Werner (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Raul Rangel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56226 ) Change subject: thread: Add missing static inline ...................................................................... Patch Set 4: (1 comment) File src/include/thread.h: https://review.coreboot.org/c/coreboot/+/56226/comment/888c9f90_c28cfdc1 PS4, Line 65: return -1; nit: I would consider making the thread_run variations call dead_code() rather than just return -1, because they shouldn't be called in the first place when threads aren't enabled. (For the other stuff like cooperate and yield I think it makes sense to keep them as silent no-ops.) -- To view, visit https://review.coreboot.org/c/coreboot/+/56226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3 Gerrit-Change-Number: 56226 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 14 Jul 2021 22:45:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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