coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/picasso: add missing banks to mca_bank_name array
by Felix Held (Code Review) 14 Jul '21

14 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56273 ) Change subject: soc/amd/picasso: add missing banks to mca_bank_name array ...................................................................... soc/amd/picasso: add missing banks to mca_bank_name array Also use array indices for the initialization. TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16 Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/mca.c 1 file changed, 23 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 23d7b61..fcc9d3e 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -135,14 +135,29 @@ } static const char *const mca_bank_name[] = { - "Load-store unit", - "Instruction fetch unit", - "L2 cache unit", - "Decode unit", - "", - "Execution unit", - "Floating point unit", - "L3 cache unit" + [0] = "Load-store unit", + [1] = "Instruction fetch unit", + [2] = "L2 cache unit", + [3] = "Decode unit", + [4] = "", + [5] = "Execution unit", + [6] = "Floating point unit", + [7] = "L3 cache unit", + [8] = "L3 cache unit", + [9] = "L3 cache unit", + [10] = "L3 cache unit", + [11] = "L3 cache unit", + [12] = "L3 cache unit", + [13] = "L3 cache unit", + [14] = "L3 cache unit", + [15] = "UMC", + [16] = "UMC", + [17] = "SMU", + [18] = "PSP", + [19] = "PB", + [20] = "CS", + [21] = "CS", + [22] = "PIE", }; static void mca_print_error(unsigned int bank) -- To view, visit https://review.coreboot.org/c/coreboot/+/56273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Gerrit-Change-Number: 56273 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56322 ) Change subject: soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware ...................................................................... soc/amd/common/block/lpc/spi_dma: Add ability to verify SPI DMA hardware The SPI DMA controller was not completely functional prior to RN/CZN. This code can be used to sanity check the DMA hardware. BUG=b:179699789 TEST=Boot guybrush with VERIFY=1 and make sure no DMA errors occur. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 --- M src/soc/amd/common/block/lpc/spi_dma.c 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/56322/1 diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c index 00cd593..cd3958b 100644 --- a/src/soc/amd/common/block/lpc/spi_dma.c +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -13,9 +13,16 @@ #include <soc/pci_devs.h> #include <spi_flash.h> #include <string.h> +#include <lib.h> #include <thread.h> #include <types.h> +/* + * Set to 1 to verify the buffer contents after the DMA transaction. + * This is helpful in building confidence in the SPI DMA controller. + */ +#define VERIFY_BUFFER 0 + /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL - CONFIG_ROM_SIZE)) @@ -119,6 +126,9 @@ ctrl |= LPC_ROM_DMA_CTRL_ERROR; /* Clear error */ ctrl |= LPC_ROM_DMA_CTRL_START; + if (VERIFY_BUFFER) + memset(transaction->destination, 0xFC, transaction->transfer_size); + pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, ctrl); } @@ -135,6 +145,20 @@ if (spi_dma_has_error()) return false; + if (VERIFY_BUFFER) { + uint8_t *mmap = + spi_dma_mmap(rd, transaction->source, transaction->transfer_size); + if (memcmp(mmap, transaction->destination, transaction->transfer_size)) { + printk(BIOS_ERR, "We had a DMA error!!!\n"); + hexdump(mmap, transaction->transfer_size); + printk(BIOS_ERR, "---------------------\n"); + hexdump(transaction->destination, transaction->transfer_size); + die("---------------------\n"); + } else { + printk(BIOS_DEBUG, "Verification successful\n"); + } + } + transaction->destination += transaction->transfer_size; transaction->source += transaction->transfer_size; transaction->remaining -= transaction->transfer_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/56322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dd54cab86ad31b135a93d4667df346c60357337 Gerrit-Change-Number: 56322 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Yield after completing transaction
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

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Change in coreboot[master]: x86/smp/spinlock: Disable thread coop when taking spinlock
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56320 ) Change subject: x86/smp/spinlock: Disable thread coop when taking spinlock ...................................................................... x86/smp/spinlock: Disable thread coop when taking spinlock Switching threads while holding a spinlock can lead to a deadlock. This happens if you have two thread trying to print to the serial console because the uart code uses udelay. BUG=b:179699789 TEST=Boot guybrush and no longer see a deadlock when printing to console from a second thread. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1b929070b7f175965d4f37be693462fef26be052 --- M src/arch/x86/include/arch/smp/spinlock.h 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/56320/1 diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h index 799ac2c..1eeb510 100644 --- a/src/arch/x86/include/arch/smp/spinlock.h +++ b/src/arch/x86/include/arch/smp/spinlock.h @@ -3,12 +3,15 @@ #ifndef ARCH_SMP_SPINLOCK_H #define ARCH_SMP_SPINLOCK_H +#include <thread.h> + /* * Your basic SMP spinlocks, allowing only a single CPU anywhere */ typedef struct { volatile unsigned int lock; + bool coop; } spinlock_t; #define SPIN_LOCK_UNLOCKED { 1 } @@ -54,10 +57,19 @@ __asm__ __volatile__( spin_lock_string : "=m" (lock->lock) : : "memory"); + + lock->coop = thread_coop_enabled(); + + /* Switching contexts while holding a spinlock will lead to deadlocks */ + thread_prevent_coop(); + } static __always_inline void spin_unlock(spinlock_t *lock) { + if (lock->coop) + thread_cooperate(); + __asm__ __volatile__( spin_unlock_string : "=m" (lock->lock) : : "memory"); -- To view, visit https://review.coreboot.org/c/coreboot/+/56320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b929070b7f175965d4f37be693462fef26be052 Gerrit-Change-Number: 56320 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/thread: Add thread_coop_enabled
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56319 ) Change subject: lib/thread: Add thread_coop_enabled ...................................................................... lib/thread: Add thread_coop_enabled This method exposes if the current thread can coop. It will be used in the following patch. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I90060e21f127fb725f126163aa5b2be6b9d1d117 --- M src/include/thread.h M src/lib/thread.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56319/1 diff --git a/src/include/thread.h b/src/include/thread.h index da8ed72..1da9c01 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -43,6 +43,7 @@ * only a single place where switching may occur: a call to udelay(). */ void thread_cooperate(void); void thread_prevent_coop(void); +bool thread_coop_enabled(void); static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { @@ -70,6 +71,10 @@ } static inline void thread_cooperate(void) {} static inline void thread_prevent_coop(void) {} +static inline bool thread_coop_enabled(void) +{ + return false; +} struct cpu_info; static inline void thread_init_cpu_info_non_bsp(struct cpu_info *ci) { } #endif diff --git a/src/lib/thread.c b/src/lib/thread.c index 782a63e..9eed5e1 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -367,3 +367,15 @@ if (current != NULL) current->can_yield = 0; } + +bool thread_coop_enabled(void) +{ + struct thread *current; + + current = current_thread(); + + if (current != NULL) + return current->can_yield; + + return false; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90060e21f127fb725f126163aa5b2be6b9d1d117 Gerrit-Change-Number: 56319 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/thread: Verify threads are initialized before yielding
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56318 ) Change subject: lib/thread: Verify threads are initialized before yielding ...................................................................... lib/thread: Verify threads are initialized before yielding In hardwaremain.c we call console_init before threads_initialize. Part of setting up the uart requires calling udelay which then calls thread_yield_microseconds. Since threads have not been setup, trying to yield will result in bad things happening. This change guards the thread methods by making current_thread return NULL if the structures have not been initialized. BUG=b:179699789 TEST=Ramstage no longer hangs with serial enabled Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43 --- M src/lib/thread.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/56318/1 diff --git a/src/lib/thread.c b/src/lib/thread.c index e2280c6..782a63e 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -9,6 +9,8 @@ #include <thread.h> #include <timer.h> +static bool initialized; + static void idle_thread_init(void); /* There needs to be at least one thread to run the ramstate state machine. */ @@ -40,6 +42,9 @@ static inline struct thread *current_thread(void) { + if (!initialized) + return NULL; + return cpu_info_to_thread(cpu_info()); } @@ -265,6 +270,8 @@ free_thread(t); } + initialized = 1; + idle_thread_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/56318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43 Gerrit-Change-Number: 56318 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Start loading APOB asynchronously
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Eric Peers, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56234 to look at the new patch set (#6). Change subject: soc/amd/cezanne: Start loading APOB asynchronously ...................................................................... soc/amd/cezanne: Start loading APOB asynchronously This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This will allow the APOB to start loading while FSP-S executes. BUG=b:179699789 TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms to a few uS. Starting APOB preload APOB thread running spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536 took 0 us to acquire mutex start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536 <ramstage doing work> spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0 <more work..> waiting for thread took 0 us APOB valid copy is already in flash Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/fsp_s_params.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/56234/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea Gerrit-Change-Number: 56234 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/apob: Add support for asynchronously reading APOB_NV
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Eric Peers, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56232 to look at the new patch set (#6). Change subject: soc/amd/common/apob: Add support for asynchronously reading APOB_NV ...................................................................... soc/amd/common/apob: Add support for asynchronously reading APOB_NV This CL adds a method that can start the processes of reading the APOB from SPI. It does require more RAM in ramstage since we no longer mmap the buffer in the happy path. This will allow us to reduce our boot time by ~10ms. The SoC code will need to be updated to call start_apob_cache_read at a point where it makes sense. BUG=b:179699789 TEST=With this and the patches above I can see a 10 ms reduction in boot time on guybrush. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 --- M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/block/include/amdblocks/apob_cache.h 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56232/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 Gerrit-Change-Number: 56232 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/thread: Add thread_handle
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Julius Werner, Eric Peers, Felix Held. Hello build bot (Jenkins), Julius Werner, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56229 to look at the new patch set (#5). Change subject: lib/thread: Add thread_handle ...................................................................... lib/thread: Add thread_handle The thread_handle can be used to wait for a thread to exit. I also added a return value to the thread function that will be stored on the handle after it completes. This makes it easy for the callers to check if the thread completed successfully or had an error. The wait_for_thread method uses the handle to block until the thread completes. BUG=b:179699789 TEST=See thread_handle state update and see error code set correctly. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff --- M src/include/thread.h M src/lib/thread.c 2 files changed, 87 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/56229/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Gerrit-Change-Number: 56229 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers
by Raul Rangel (Code Review) 14 Jul '21

14 Jul '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56231 to look at the new patch set (#5). Change subject: soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers ...................................................................... soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registers Once we enable COOP_MULTITASKING, we need to guarantee that we don't have multiple threads trying to access the DMA hardware. BUG=b:179699789 TEST=Boot guybrush with APOB patches. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09 --- M src/soc/amd/common/block/lpc/spi_dma.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/56231/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09 Gerrit-Change-Number: 56231 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021