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Hello build bot (Jenkins), Julius Werner, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: lib/thread: Add mutex
......................................................................
lib/thread: Add mutex
We need a way to protect shared resources. Since we are using cooperative
multitasking the mutex implementation is pretty trivial.
The delays are implemented using a timer queue. So the task with the
next expiration date will always be at the beginning of the queue.
If a task (A) wishes to yield control to the next task (B) that is
holding onto the mutex, without encountering a delay of its own
(i.e., udelay(0)), then we need to ensure the next task (B) is at the
head of the queue. We do this by using a `0 us` delay in mutex_lock. If
we were to use anything larger than a `0 us` delay, a `udelay(0)` by the
task (A) that just unlocked the mutex will most likely not schedule the
next task (B) that was holding onto the mutex.
BUG=b:179699789
TEST=Verify thread lock and unlock.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff
---
M src/include/thread.h
M src/lib/thread.c
2 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/56230/5
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56228
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Change subject: soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
......................................................................
soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionality
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/spi_dma.c
2 files changed, 186 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56228/5
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Change subject: soc/amd/common/block/cpu/mca/mcax: print all MCAX registers
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/common/block/cpu/mca: make building the BERT support conditional
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/common/block/cpu/mca: commonize mca_check_all_banks
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/amd/common/block/cpu/mca/mca: factor out mca_skip_check
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/block/cpu/mca: move function prototypes to local header
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/*/mca: factor out common MCA/MCAX check & print functionality
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/picasso/mca: factor out mca_has_expected_bank_count
......................................................................
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