coreboot-gerrit July 2021

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Change in coreboot[master]: util/ifdtool: Add an option to set top swap block size
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Stefan Reinauer, Rizwan Qureshi, Meera Ravindranath, Sridhar Siricilla. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48471 ) Change subject: util/ifdtool: Add an option to set top swap block size ...................................................................... Patch Set 10: (4 comments) File util/ifdtool/ifdtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124289): https://review.coreboot.org/c/coreboot/+/48471/comment/1a3af3cc_71453250 PS10, Line 1091: printf("Top swap block size greater than 1MB not supported on this platform.\n"); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124289): https://review.coreboot.org/c/coreboot/+/48471/comment/fac84474_3d7fa2be PS10, Line 1094: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124289): https://review.coreboot.org/c/coreboot/+/48471/comment/4214dcc0_c2cb857a PS10, Line 1120: switch (platform){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124289): https://review.coreboot.org/c/coreboot/+/48471/comment/2b1b3445_4344a4d4 PS10, Line 1867: if (!is_valid_topswap(&new_topswap)) { suspect code indent for conditional statements (24, 40) -- To view, visit https://review.coreboot.org/c/coreboot/+/48471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I291e5f8443f00ae9a11096c13073ad4dea887fe5 Gerrit-Change-Number: 48471 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 08:17:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B
by EricR Lai (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Wu, Martin Roth, Isaac Lee, Paul Menzel. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56328 ) Change subject: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Gerrit-Change-Number: 56328 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 08:16:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Include SPD for MT53E1G32D2NP-046 WT:A and...
by Mark Hsieh (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Caveh Jalali, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56329 ) Change subject: mb/google/brya/var/gimble: Include SPD for MT53E1G32D2NP-046 WT:A and K4U6E3S4AA-MGCR ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/56329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bfc18fd42c6ff2675e6f836c2ecc9617fac3aff Gerrit-Change-Number: 56329 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 08:13:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B
by Frank Wu (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Wu, Martin Roth, Isaac Lee, Paul Menzel, EricR Lai. Hello build bot (Jenkins), Martin Roth, Kangheui Won, Isaac Lee, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56328 to look at the new patch set (#3). Change subject: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B ...................................................................... mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B Add new ram_id:1000 for memory part MT40A1G16RC-062E:B. BUG=b:193732051 TEST=Generate new spd file and build coreboot. Then boot from the DUT with new memory MT40A1G16RC-062E:B Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 --- M src/mainboard/google/zork/variants/vilboz/spd/Makefile.inc M src/mainboard/google/zork/variants/vilboz/spd/dram_id.generated.txt M src/mainboard/google/zork/variants/vilboz/spd/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56328/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Gerrit-Change-Number: 56328 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Add an option to set top swap block size
by Krishna P Bhat D (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Stefan Reinauer, Rizwan Qureshi, Meera Ravindranath, Sridhar Siricilla, Krishna P Bhat D. Hello build bot (Jenkins), Jamie Ryu, Stefan Reinauer, Rizwan Qureshi, Sugnan Prabhu S, Sridhar Siricilla, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48471 to look at the new patch set (#10). Change subject: util/ifdtool: Add an option to set top swap block size ...................................................................... util/ifdtool: Add an option to set top swap block size Add an option '-j' which takes the size of top swap boundary. This option takes the top swap block size and sets the value in descriptor when a second bootblock is to be used with top swap feature in Intel CPUs. BUG=None BRANCH=None TEST=Set topswap block size and check the offset to determine it is correctly set. Usage: ifdtool -p <platform> -j <top swap block size> ifdtool -p jsl -j 0x10000 hexdump image-drawcia.bin.new 0000140 0000 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x20000 hexdump image-drawcia.bin.new 0000140 0010 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x20000 hexdump image-drawcia.bin.new 0000140 0020 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x20000 hexdump image-drawcia.bin.new 0000140 0030 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x100000 hexdump image-drawcia.bin.new 0000140 0040 c880 8645 0600 0000 0000 0204 0058 Change-Id: I291e5f8443f00ae9a11096c13073ad4dea887fe5 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 121 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48471/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/48471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I291e5f8443f00ae9a11096c13073ad4dea887fe5 Gerrit-Change-Number: 48471 Gerrit-PatchSet: 10 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Add an option to set top swap block size
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Stefan Reinauer, Rizwan Qureshi, Meera Ravindranath, Sridhar Siricilla, Krishna P Bhat D. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48471 ) Change subject: util/ifdtool: Add an option to set top swap block size ...................................................................... Patch Set 9: (5 comments) File util/ifdtool/ifdtool.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124281): https://review.coreboot.org/c/coreboot/+/48471/comment/ff9d1307_c2b910db PS9, Line 1071: if(((platform != PLATFORM_TGL) && (*topswap_size > 1*MiB)) || ((platform != PLATFORM_ADL) line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124281): https://review.coreboot.org/c/coreboot/+/48471/comment/531013ec_ca63ce84 PS9, Line 1071: if(((platform != PLATFORM_TGL) && (*topswap_size > 1*MiB)) || ((platform != PLATFORM_ADL) space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124281): https://review.coreboot.org/c/coreboot/+/48471/comment/b312e078_aa2d49e6 PS9, Line 1076: else { else should follow close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124281): https://review.coreboot.org/c/coreboot/+/48471/comment/33e2e357_22c946bc PS9, Line 1122: switch (platform){ space required before the open brace '{' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124281): https://review.coreboot.org/c/coreboot/+/48471/comment/2b18bffe_980318f6 PS9, Line 1854: if (!is_valid_topswap(&new_topswap)) { suspect code indent for conditional statements (24, 40) -- To view, visit https://review.coreboot.org/c/coreboot/+/48471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I291e5f8443f00ae9a11096c13073ad4dea887fe5 Gerrit-Change-Number: 48471 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:58:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Michał Żygowski, Marshall Dawson, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/c03fa52c_94d5c666 PS3, Line 14: looks_like_fsp_header > > irrespective of you are considering this new API or not, inclusion of MultiSi API into your EDK2 […] i believe upper boundary check is always prescribed isn't it. we don't know what for those additional bytes are being introduced? Assume for this case, if we really want to discard those additional 4 bytes of MultiSi API then can't we check if FSP_INFO_HEADER.HeaderRevision < 5 then FSP_INFO_HEADER..HeaderLength - 4 == 72 would help to find the integrity of the FSP header with FSP 2.0 isn't it ? (in this process we actually knew what we are discarding) vs a minimal boundary check? If FSP_INFO_HEADER.HeaderRevision >= 5 then we are expecting MultiSi is added and in that case FSP_INFO_HEADER..HeaderLength should be 76 with FSP 2.2 spec? Sorry may be I'm thinking a loud about how someone can explode the situation and introduced few more APIs or some data fields without bootloader knowledge (may be an imaginary situation unless its actually appears) -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:55:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: southbridge/intel: Update top swap block size using ifdtool option
by Meera Ravindranath (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Meera Ravindranath, Sridhar Siricilla, Patrick Rudolph. Meera Ravindranath has uploaded a new patch set (#9) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/48472 ) Change subject: southbridge/intel: Update top swap block size using ifdtool option ...................................................................... southbridge/intel: Update top swap block size using ifdtool option Currently the INTEL_TOP_SWAP_BOOTBLOCK_SIZE is used in the context of cbfstool/ifittool to add top swap boot block and update fit pointers. The top-swap size definition is in 2 places i.e., descriptor and Kconfig, which will have to be aligned by the developer and can be missed. To address this issue, use the option (-j) added in ifdtool to set the top-swap size to whatever value is specified by INTEL_TOP_SWAP_BOOTBLOCK_SIZE. BUG=None BRANCH=None TEST=emerge-dedede coreboot chromeos-bootimage. When INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000, cbfstool image-drawcia.bin print -r COREBOOT ... bootblock 0x3d7fc0 bootblock 131072 none hexdump image-drawcia.bin.new 0000140 0000 c880 8645 0600 0000 0000 0204 0058 When INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x20000, cbfstool image-drawcia.bin print -r COREBOOT ... bootblock 0x3d7fc0 bootblock 262144 none hexdump image-drawcia.bin.new 0000140 0010 c880 8645 0600 0000 0000 0204 0058 Change-Id: Ibd13c36d5754778db2f8996dbd5aa681f28bbb6c Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/southbridge/intel/common/firmware/Makefile.inc 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/48472/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/48472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd13c36d5754778db2f8996dbd5aa681f28bbb6c Gerrit-Change-Number: 48472 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/ifdtool: Add an option to set top swap block size
by Meera Ravindranath (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Stefan Reinauer, Rizwan Qureshi, Sridhar Siricilla. Meera Ravindranath has uploaded a new patch set (#9) to the change originally created by Krishna P Bhat D. ( https://review.coreboot.org/c/coreboot/+/48471 ) Change subject: util/ifdtool: Add an option to set top swap block size ...................................................................... util/ifdtool: Add an option to set top swap block size Add an option '-j' which takes the size of top swap boundary. This option takes the top swap block size and sets the value in descriptor when a second bootblock is to be used with top swap feature in Intel CPUs. BUG=None BRANCH=None TEST=Set topswap block size and check the offset to determine it is correctly set. Usage: ifdtool -p <platform> -j <top swap block size> ifdtool -p jsl -j 0x10000 hexdump image-drawcia.bin.new 0000140 0000 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x20000 hexdump image-drawcia.bin.new 0000140 0010 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x20000 hexdump image-drawcia.bin.new 0000140 0020 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x20000 hexdump image-drawcia.bin.new 0000140 0030 c880 8645 0600 0000 0000 0204 0058 ifdtool -p jsl -j 0x100000 hexdump image-drawcia.bin.new 0000140 0040 c880 8645 0600 0000 0000 0204 0058 Change-Id: I291e5f8443f00ae9a11096c13073ad4dea887fe5 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 112 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48471/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/48471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I291e5f8443f00ae9a11096c13073ad4dea887fe5 Gerrit-Change-Number: 48471 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B
by Kangheui Won (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Frank Wu, Martin Roth, Isaac Lee, Paul Menzel, EricR Lai. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56328 ) Change subject: mb/google/zork/var/vilboz: Add new memory MT40A1G16RC-062E:B ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Not sure if char limit also applies to this long command. Other than that, lgtm. -- To view, visit https://review.coreboot.org/c/coreboot/+/56328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0 Gerrit-Change-Number: 56328 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 07:49:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2021