coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: soc/intel/jasperlake: add pcie modphy settings
by Jamie Chen (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jamie Chen. Hello Jamie Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56336 to review the following change. Change subject: soc/intel/jasperlake: add pcie modphy settings ...................................................................... soc/intel/jasperlake: add pcie modphy settings This patch expose some pcie modphy UPDs/configuration to be filled from devicetree. It's for fine tune pcie port signal quality. BUG=b:192716633 BRANCH=NONE TEST=build dedede variant coreboot with fw_debug enable and chekc if these settings have been changed successfully on fsp debug log. Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/romstage/fsp_params.c 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/56336/1 diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 36e9a13..1e6a300 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -101,6 +101,22 @@ uint8_t PchHdaIDispLinkFrequency; uint8_t PchHdaIDispCodecDisconnect; + /* PCIe ModPHY related */ + uint8_t PchPcieHsioRxSetCtleEnable[24]; + uint8_t PchPcieHsioRxSetCtle[24]; + uint8_t PchPcieHsioTxGen1DownscaleAmpEnable[24]; + uint8_t PchPcieHsioTxGen1DownscaleAmp[24]; + uint8_t PchPcieHsioTxGen2DownscaleAmpEnable[24]; + uint8_t PchPcieHsioTxGen2DownscaleAmp[24]; + uint8_t PchPcieHsioTxGen3DownscaleAmpEnable[24]; + uint8_t PchPcieHsioTxGen3DownscaleAmp[24]; + uint8_t PchPcieHsioTxGen1DeEmphEnable[24]; + uint8_t PchPcieHsioTxGen1DeEmph[24]; + uint8_t PchPcieHsioTxGen2DeEmph3p5Enable[24]; + uint8_t PchPcieHsioTxGen2DeEmph3p5[24]; + uint8_t PchPcieHsioTxGen2DeEmph6p0Enable[24]; + uint8_t PchPcieHsioTxGen2DeEmph6p0[24]; + /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index c1208e3..4c2c925 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -27,6 +27,30 @@ m_cfg->SaGv = config->SaGv; m_cfg->RMT = config->RMT; + /* PCIe ModPhy configuration */ + for (i = 0; i < ARRAY_SIZE(config->PchPcieHsioRxSetCtleEnable); i++) { + if (config->PchPcieHsioRxSetCtleEnable[i]) + m_cfg->PchPcieHsioRxSetCtle[i] = config->PchPcieHsioRxSetCtle[i]; + if (config->PchPcieHsioTxGen1DownscaleAmpEnable[i]) + m_cfg->PchPcieHsioTxGen1DownscaleAmp[i] = + config->PchPcieHsioTxGen1DownscaleAmp[i]; + if (config->PchPcieHsioTxGen2DownscaleAmpEnable[i]) + m_cfg->PchPcieHsioTxGen2DownscaleAmp[i] = + config->PchPcieHsioTxGen2DownscaleAmp[i]; + if (config->PchPcieHsioTxGen3DownscaleAmp[i]) + m_cfg->PchPcieHsioTxGen3DownscaleAmp[i] = + config->PchPcieHsioTxGen3DownscaleAmp[i]; + if (config->PchPcieHsioTxGen1DeEmphEnable[i]) + m_cfg->PchPcieHsioTxGen1DeEmph[i] = + config->PchPcieHsioTxGen1DeEmph[i]; + if (config->PchPcieHsioTxGen2DeEmph3p5Enable[i]) + m_cfg->PchPcieHsioTxGen2DeEmph3p5[i] = + config->PchPcieHsioTxGen2DeEmph3p5[i]; + if (config->PchPcieHsioTxGen2DeEmph6p0Enable[i]) + m_cfg->PchPcieHsioTxGen2DeEmph6p0[i] = + config->PchPcieHsioTxGen2DeEmph6p0[i]; + } + /* PCIe root port configuration */ for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) -- To view, visit https://review.coreboot.org/c/coreboot/+/56336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Gerrit-Change-Number: 56336 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/starlabs: Add Star Labs ITE 5570E support
by Sean Rhodes (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55263 ) Change subject: ec/starlabs: Add Star Labs ITE 5570E support ...................................................................... Patch Set 22: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55263/comment/689b866b_dc8615b5 PS3, Line 9: Support for Star Labs labtop series EC > IO Port 4e Done File src/ec/starlabs/it5570/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/55263/comment/57401a48_8b93ece0 PS4, Line 45: // Store (0x03, \_SB.PCI0.GFX0.CLID) > ¯\_(ツ)_/¯ Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52287cd3c7606aa210621bb491665410c6fcab96 Gerrit-Change-Number: 55263 Gerrit-PatchSet: 22 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 10:38:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <admin(a)starlabs.systems> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel: Add dedicated file to grow Intel CPUIDs
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Furquan Shaikh, Mariusz Szafrański, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Morgan Jang, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56333 ) Change subject: cpu/intel: Add dedicated file to grow Intel CPUIDs ...................................................................... Patch Set 2: (1 comment) File src/cpu/intel/haswell/haswell.h: PS1: > I wouldn't change Haswell. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/56333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Gerrit-Change-Number: 56333 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 10:12:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel: Add dedicated file to grow Intel CPUIDs
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Furquan Shaikh, Mariusz Szafrański, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Subrata Banik, Michal Motyl, Morgan Jang, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56333 to look at the new patch set (#2). Change subject: cpu/intel: Add dedicated file to grow Intel CPUIDs ...................................................................... cpu/intel: Add dedicated file to grow Intel CPUIDs This patch removes all local `CPUID_` macros from SoC directories and creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC users are expected to add any new CPUID support into cpu_ids.h and include 'cpu/intel/cpu_ids.h' into respective files that look for `CPUID_` macro. Note: CPUIDs for HSW, BDW and Quark are still inside the respective directory. Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/denverton_ns/include/soc/cpu.h M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h M src/soc/intel/xeon_sp/skx/include/soc/cpu.h 5 files changed, 62 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/56333/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Gerrit-Change-Number: 56333 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/intel: Add dedicated file to grow Intel CPUIDs
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56335 ) Change subject: cpu/intel: Add dedicated file to grow Intel CPUIDs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/56335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fcd9b94da3f3779917220ea32bd5824bc7f7b9c Gerrit-Change-Number: 56335 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: cpu/intel: Add dedicated file to grow Intel CPUIDs
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56335 ) Change subject: cpu/intel: Add dedicated file to grow Intel CPUIDs ...................................................................... cpu/intel: Add dedicated file to grow Intel CPUIDs This patch removes all local `CPUID_` macros from SoC directories and creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC users are expected to add any new CPUID support into cpu_ids.h and include 'cpu/intel/cpu_ids.h' into respective files that look for `CPUID_` macro. Note: CPUIDs for HSW, BDW and Quark are still inside the respective directory. Change-Id: I6fcd9b94da3f3779917220ea32bd5824bc7f7b9c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/denverton_ns/include/soc/cpu.h M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h M src/soc/intel/xeon_sp/skx/include/soc/cpu.h 5 files changed, 62 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/56335/1 diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h new file mode 100644 index 0000000..7094f6c --- /dev/null +++ b/src/include/cpu/intel/cpu_ids.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef CPU_INTEL_CPU_IDS_H +#define CPU_INTEL_CPU_IDS_H + +/* Supported CPUIDs for different Intel CPU */ + +#define CPUID_DENVERTON_A0_A1 0x506f0 +#define CPUID_DENVERTON_B0 0x506f1 +#define CPUID_COOPERLAKE_SP_A0 0x5065a +#define CPUID_COOPERLAKE_SP_A1 0x5065b +#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 +#define CPUID_SKYLAKE_SP_B0 0x506f1 +#define CPUID_SKYLAKE_SP_4 0x50654 +#define CPUID_SKYLAKE_C0 0x406e2 +#define CPUID_SKYLAKE_D0 0x406e3 +#define CPUID_SKYLAKE_HQ0 0x506e1 +#define CPUID_SKYLAKE_HR0 0x506e3 +#define CPUID_KABYLAKE_G0 0x406e8 +#define CPUID_KABYLAKE_H0 0x806e9 +#define CPUID_KABYLAKE_Y0 0x806ea +#define CPUID_KABYLAKE_HA0 0x506e8 +#define CPUID_KABYLAKE_HB0 0x906e9 +#define CPUID_CANNONLAKE_A0 0x60660 +#define CPUID_CANNONLAKE_B0 0x60661 +#define CPUID_CANNONLAKE_C0 0x60662 +#define CPUID_CANNONLAKE_D0 0x60663 +#define CPUID_APOLLOLAKE_A0 0x506c8 +#define CPUID_APOLLOLAKE_B0 0x506c9 +#define CPUID_APOLLOLAKE_E0 0x506ca +#define CPUID_GLK_A0 0x706a0 +#define CPUID_GLK_B0 0x706a1 +#define CPUID_GLK_R0 0x706a8 +#define CPUID_WHISKEYLAKE_V0 0x806ec +#define CPUID_WHISKEYLAKE_W0 0x806eb +#define CPUID_COFFEELAKE_U0 0x906ea +#define CPUID_COFFEELAKE_B0 0x906eb +#define CPUID_COFFEELAKE_P0 0x906ec +#define CPUID_COFFEELAKE_R0 0x906ed +#define CPUID_ICELAKE_A0 0x706e0 +#define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE_A0 0x906c0 +#define CPUID_COMETLAKE_U_A0 0xa0660 +#define CPUID_COMETLAKE_U_K0_S0 0xa0661 +#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 +#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 +#define CPUID_TIGERLAKE_A0 0x806c0 +#define CPUID_TIGERLAKE_B0 0x806c1 +#define CPUID_ELKHARTLAKE_A0 0x90660 +#define CPUID_ELKHARTLAKE_B0 0x90661 +#define CPUID_ALDERLAKE_S_A0 0x90670 +#define CPUID_ALDERLAKE_A0 0x906a0 +#define CPUID_ALDERLAKE_A1 0x906a1 +#define CPUID_ALDERLAKE_A2 0x906a2 + +#endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index dd2653b..8a413ea 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -3,51 +3,10 @@ #ifndef SOC_INTEL_COMMON_BLOCK_MP_INIT_H #define SOC_INTEL_COMMON_BLOCK_MP_INIT_H +#include <cpu/intel/cpu_ids.h> #include <device/device.h> /* Supported CPUIDs for different SOCs */ -#define CPUID_SKYLAKE_C0 0x406e2 -#define CPUID_SKYLAKE_D0 0x406e3 -#define CPUID_SKYLAKE_HQ0 0x506e1 -#define CPUID_SKYLAKE_HR0 0x506e3 -#define CPUID_KABYLAKE_G0 0x406e8 -#define CPUID_KABYLAKE_H0 0x806e9 -#define CPUID_KABYLAKE_Y0 0x806ea -#define CPUID_KABYLAKE_HA0 0x506e8 -#define CPUID_KABYLAKE_HB0 0x906e9 -#define CPUID_CANNONLAKE_A0 0x60660 -#define CPUID_CANNONLAKE_B0 0x60661 -#define CPUID_CANNONLAKE_C0 0x60662 -#define CPUID_CANNONLAKE_D0 0x60663 -#define CPUID_APOLLOLAKE_A0 0x506c8 -#define CPUID_APOLLOLAKE_B0 0x506c9 -#define CPUID_APOLLOLAKE_E0 0x506ca -#define CPUID_GLK_A0 0x706a0 -#define CPUID_GLK_B0 0x706a1 -#define CPUID_GLK_R0 0x706a8 -#define CPUID_WHISKEYLAKE_V0 0x806ec -#define CPUID_WHISKEYLAKE_W0 0x806eb -#define CPUID_COFFEELAKE_U0 0x906ea -#define CPUID_COFFEELAKE_B0 0x906eb -#define CPUID_COFFEELAKE_P0 0x906ec -#define CPUID_COFFEELAKE_R0 0x906ed -#define CPUID_ICELAKE_A0 0x706e0 -#define CPUID_ICELAKE_B0 0x706e1 -#define CPUID_JASPERLAKE_A0 0x906c0 -#define CPUID_COMETLAKE_U_A0 0xa0660 -#define CPUID_COMETLAKE_U_K0_S0 0xa0661 -#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 -#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 -#define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 -#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 -#define CPUID_TIGERLAKE_A0 0x806c0 -#define CPUID_TIGERLAKE_B0 0x806c1 -#define CPUID_ELKHARTLAKE_A0 0x90660 -#define CPUID_ELKHARTLAKE_B0 0x90661 -#define CPUID_ALDERLAKE_S_A0 0x90670 -#define CPUID_ALDERLAKE_A0 0x906a0 -#define CPUID_ALDERLAKE_A1 0x906a1 -#define CPUID_ALDERLAKE_A2 0x906a2 /* * MP Init callback function to Find CPU Topology. This function is common * among all SOCs and thus its in Common CPU block. diff --git a/src/soc/intel/denverton_ns/include/soc/cpu.h b/src/soc/intel/denverton_ns/include/soc/cpu.h index 0f9d3ace..f4b0d3c 100644 --- a/src/soc/intel/denverton_ns/include/soc/cpu.h +++ b/src/soc/intel/denverton_ns/include/soc/cpu.h @@ -3,6 +3,8 @@ #ifndef _CPU_INTEL_DENVERTON_NS_H #define _CPU_INTEL_DENVERTON_NS_H +#include <cpu/intel/cpu_ids.h> + int get_cpu_count(void); #ifndef __ASSEMBLER__ @@ -14,10 +16,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -/* Denverton-NS CPUID */ -#define CPUID_DENVERTON_A0_A1 0x506f0 -#define CPUID_DENVERTON_B0 0x506f1 - #define MSR_CORE_THREAD_COUNT 0x35 #define CORE_BIT_MSK 0x1 #define MCH_BAR_CORE_EXISTS_MASK 0x7164 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 716fe29e..d00c27f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -4,11 +4,9 @@ #define _SOC_CPU_H #include <device/device.h> +#include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h> -#define CPUID_COOPERLAKE_SP_A0 0x5065a -#define CPUID_COOPERLAKE_SP_A1 0x5065b - void cpx_init_cpus(struct device *dev); #endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index 433598b..ef712ab 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -4,13 +4,9 @@ #define _SOC_CPU_H_ #include <device/device.h> +#include <cpu/intel/cpu_ids.h> #include <cpu/x86/msr.h> -/* SKXSP CPUID */ -#define CPUID_SKYLAKE_SP_A0_A1 0x506f0 -#define CPUID_SKYLAKE_SP_B0 0x506f1 -#define CPUID_SKYLAKE_SP_4 0x50654 - /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 -- To view, visit https://review.coreboot.org/c/coreboot/+/56335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fcd9b94da3f3779917220ea32bd5824bc7f7b9c Gerrit-Change-Number: 56335 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: cpu/intel: Add dedicated file to grow Intel CPUIDs
by Angel Pons (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Furquan Shaikh, Mariusz Szafrański, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Subrata Banik, Michal Motyl, Morgan Jang, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56333 ) Change subject: cpu/intel: Add dedicated file to grow Intel CPUIDs ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/haswell/haswell.h: PS1: > nothing specific for common code, attempted to move all IA CPUIDs in a common location outside the s […] I wouldn't change Haswell. Putting these CPUIDs in common code moves them away from the code that uses them without any advantages. -- To view, visit https://review.coreboot.org/c/coreboot/+/56333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Gerrit-Change-Number: 56333 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:56:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mainboard/starlabs: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Sean Rhodes, Nico Huber, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56088 ) Change subject: mainboard/starlabs: Add Star Labs labtop series ...................................................................... Patch Set 41: (1 comment) File src/mainboard/starlabs/labtop/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124300): https://review.coreboot.org/c/coreboot/+/56088/comment/b3dbcf69_94d2ead9 PS41, Line 98: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/56088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Gerrit-Change-Number: 56088 Gerrit-PatchSet: 41 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:53:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cannonlake mainboards: Set PMC as hidden in devicetree
by Michael Niewöhner (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Matt DeVillier, Jeremy Soller, Tim Wawrzynczak, Karthik Ramasubramanian. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56008 ) Change subject: cannonlake mainboards: Set PMC as hidden in devicetree ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > We do, to reserve the P2SB BAR. […] There should be a warning (error?) when it's `on` but hidden by the FSP, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/56008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355 Gerrit-Change-Number: 56008 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:52:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: console: Handle verstage as "first non-bootblock stage"
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Nico Huber, Julius Werner. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56210 ) Change subject: console: Handle verstage as "first non-bootblock stage" ...................................................................... Patch Set 1: (1 comment) File src/console/init.c: https://review.coreboot.org/c/coreboot/+/56210/comment/b1ba9869_fad730a3 PS1, Line 15: #endif > > For one, some stages are _pretty_ packed, e.g. verstage on google/veyron. […] Given the back and forth here I'm thinking of making all this explicit, even though I dislike options proliferation: Kconfig options "NO_(BOOTBLOCK|VERSTAGE|ROMSTAGE|RAMSTAGE)_CONSOLE(_OVERRIDE|)" to disable everything per stage or to disable the overrides based on external factors. As an example, rk3288 would enable NO_VERSTAGE_CONSOLE_OVERRIDE by default for space reasons, arch/arm* could default to NO_BOOTBLOCK_CONSOLE_OVERRIDE because we can't trust CBFS to be flexible enough around there, and users could vary per-board or per-build as desired. -- To view, visit https://review.coreboot.org/c/coreboot/+/56210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I494a33483e306a049aa0c8137a118644fc28177e Gerrit-Change-Number: 56210 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 09:52:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021