coreboot-gerrit July 2021

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by Paul Menzel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add board ...................................................................... Patch Set 4: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56339/comment/48a1b78d_7cb2efc7 PS2, Line 7: asrock/e3c246d4i: Add board Maybe: > mb/asrock/e3c246d4i: Add Intel Coffee Lake board https://review.coreboot.org/c/coreboot/+/56339/comment/020fe3de_6bc47e26 PS2, Line 9: Openbmc OpenBMC https://review.coreboot.org/c/coreboot/+/56339/comment/705272b3_8499f6b9 PS2, Line 11: It’d be great if you could document if you wrote this from scratch or used some other board as template. https://review.coreboot.org/c/coreboot/+/56339/comment/5756c155_ffc2214c PS2, Line 21: options Option ROM? Patchset: PS4: Awesome! File src/mainboard/asrock/e3c246d4i/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56339/comment/068fe1a1_4f5a09d0 PS2, Line 47: device pci 12.0 on end # Thermal Subsystem Should the comments be aligned? File src/mainboard/asrock/e3c246d4i/dsdt.asl: https://review.coreboot.org/c/coreboot/+/56339/comment/2aa35d5c_dacad76a PS2, Line 27: Please remove the blank line. -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jul 2021 13:20:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56339 to look at the new patch set (#4). Change subject: asrock/e3c246d4i: Add board ...................................................................... asrock/e3c246d4i: Add board This board has upstream Openbmc support so it's quite nice to develop on. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running options of the 10G NICs TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,556 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add board ...................................................................... Patch Set 3: (4 comments) File src/mainboard/asrock/e3c246d4i/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124311): https://review.coreboot.org/c/coreboot/+/56339/comment/78c18c7f_f0fa4ae5 PS3, Line 10: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124311): https://review.coreboot.org/c/coreboot/+/56339/comment/190c1afe_459cea66 PS3, Line 15: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124311): https://review.coreboot.org/c/coreboot/+/56339/comment/15dc637f_069abba4 PS3, Line 20: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124311): https://review.coreboot.org/c/coreboot/+/56339/comment/0762e15c_44b69947 PS3, Line 25: { that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jul 2021 13:18:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56339 to look at the new patch set (#3). Change subject: asrock/e3c246d4i: Add board ...................................................................... asrock/e3c246d4i: Add board This board has upstream Openbmc support so it's quite nice to develop on. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running options of the 10G NICs TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,560 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add board ...................................................................... Patch Set 2: (6 comments) File src/mainboard/asrock/e3c246d4i/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124310): https://review.coreboot.org/c/coreboot/+/56339/comment/19af758f_5731a562 PS2, Line 8: the hardware starting from closest to the cpu. */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124310): https://review.coreboot.org/c/coreboot/+/56339/comment/3c9b8d00_9175953f PS2, Line 8: the hardware starting from closest to the cpu. */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124310): https://review.coreboot.org/c/coreboot/+/56339/comment/b4501043_d69cb43a PS2, Line 10: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124310): https://review.coreboot.org/c/coreboot/+/56339/comment/5c7ee6eb_061a2fc4 PS2, Line 15: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124310): https://review.coreboot.org/c/coreboot/+/56339/comment/d178741b_b44acf45 PS2, Line 20: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124310): https://review.coreboot.org/c/coreboot/+/56339/comment/d122fe1e_a83818ce PS2, Line 25: { that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jul 2021 13:09:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add board ...................................................................... asrock/e3c246d4i: Add board This board has upstream Openbmc support so it's quite nice to develop on. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running options of the 10G NICs TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,560 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: add pcie modphy settings
by Jamie Chen (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jamie Chen, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56336 to look at the new patch set (#2). Change subject: soc/intel/jasperlake: add pcie modphy settings ...................................................................... soc/intel/jasperlake: add pcie modphy settings This patch adds device tree settings to control pcie modphy tuning FSP UPDs. With this patch, the pcie modphy can be tuned per board. BUG=b:192716633 BRANCH=NONE TEST=build dedede variant coreboot with fw_debug enable and check if these settings have been changed successfully on fsp debug log. Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/romstage/fsp_params.c 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/56336/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Gerrit-Change-Number: 56336 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by build bot (Jenkins) (Code Review) 15 Jul '21

15 Jul '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add board ...................................................................... Patch Set 1: (6 comments) File src/mainboard/asrock/e3c246d4i/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124309): https://review.coreboot.org/c/coreboot/+/56339/comment/8f24ed82_f553744b PS1, Line 8: the hardware starting from closest to the cpu. */ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124309): https://review.coreboot.org/c/coreboot/+/56339/comment/486ff209_5595a7d5 PS1, Line 8: the hardware starting from closest to the cpu. */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124309): https://review.coreboot.org/c/coreboot/+/56339/comment/a63caf28_7b9913c2 PS1, Line 10: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124309): https://review.coreboot.org/c/coreboot/+/56339/comment/3dbf534e_ecc338c1 PS1, Line 15: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124309): https://review.coreboot.org/c/coreboot/+/56339/comment/748a3ba0_305812cc PS1, Line 20: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-124309): https://review.coreboot.org/c/coreboot/+/56339/comment/bd9bf3f4_e5ddf532 PS1, Line 25: { that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 13:04:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add board ...................................................................... asrock/e3c246d4i: Add board This board has upstream Openbmc support so it's quite nice to develop on. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running options of the 10G NICs TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,560 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/1 diff --git a/src/mainboard/asrock/e3c246d4i/Kconfig b/src/mainboard/asrock/e3c246d4i/Kconfig new file mode 100644 index 0000000..ea330b2 --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/Kconfig @@ -0,0 +1,50 @@ +if BOARD_ASROCK_E3C246D4I + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SUPERIO_ASPEED_AST2400 + select DRIVERS_ASPEED_AST_COMMON + select DRIVERS_ASPEED_AST2050 + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE + +config MAINBOARD_DIR + string + default "asrock/e3c246d4i" + +config MAINBOARD_PART_NUMBER + string + default "e3c246d4i" + +config CBFS_SIZE + hex + default 0x800000 + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +# 0 - 0x3f8: Hardware COM1 port +# 1 - 0x2f8: SOL console on BMC +config UART_FOR_CONSOLE + int + default 1 + +config MAX_CPUS + int + default 16 + +config DIMM_MAX + int + default 4 + +endif diff --git a/src/mainboard/asrock/e3c246d4i/Kconfig.name b/src/mainboard/asrock/e3c246d4i/Kconfig.name new file mode 100644 index 0000000..6eac01e --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_E3C246D4I + bool "e3c246d4i" diff --git a/src/mainboard/asrock/e3c246d4i/Makefile.inc b/src/mainboard/asrock/e3c246d4i/Makefile.inc new file mode 100644 index 0000000..771d53e --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/Makefile.inc @@ -0,0 +1,7 @@ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio.c + +ramstage-y += ramstage.c +ramstage-y += gpio.c diff --git a/src/mainboard/asrock/e3c246d4i/board_info.txt b/src/mainboard/asrock/e3c246d4i/board_info.txt new file mode 100644 index 0000000..91e8d03 --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: oryp5 +Category: laptop +Release year: 2019 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/asrock/e3c246d4i/bootblock.c b/src/mainboard/asrock/e3c246d4i/bootblock.c new file mode 100644 index 0000000..82ec2a8 --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/bootblock.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> +#include <mainboard/gpio.h> + +#define ASPEED_SIO_PORT 0x4E + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = + PNP_DEV(ASPEED_SIO_PORT, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/e3c246d4i/devicetree.cb b/src/mainboard/asrock/e3c246d4i/devicetree.cb new file mode 100644 index 0000000..fdb15c7 --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/devicetree.cb @@ -0,0 +1,163 @@ +chip soc/intel/cannonlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + + register "DisableHeciRetry" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Serial IRQ Continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + # FIXME: Refine PCIe clock source/request settings + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + register "PcieClkSrcUsage[6]" = "0x80" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieClkSrcUsage[8]" = "0x80" + register "PcieClkSrcUsage[9]" = "0x80" + register "PcieClkSrcUsage[10]" = "0x80" + register "PcieClkSrcUsage[11]" = "0x80" + register "PcieClkSrcUsage[12]" = "0x80" + register "PcieClkSrcUsage[13]" = "0x80" + register "PcieClkSrcUsage[14]" = "0x80" + register "PcieClkSrcUsage[15]" = "0x80" + + device domain 0 on + subsystemid 0x1849 0x3ec6 inherit + device pci 00.0 on end # Host Bridge + device pci 01.0 on # GPU Port + end + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + # TODO USB2 No clue... + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + # TODO USB3 No clue + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Shared SRAM + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 on end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1b.0 on # PCI Express Port 17 + register "PcieRpEnable[16]" = "1" + register "PcieRpLtrEnable[16]" = "1" + end + device pci 1b.1 off end # PCI Express Port 18 + device pci 1b.2 off end # PCI Express Port 19 + device pci 1b.3 off end # PCI Express Port 20 + device pci 1b.4 on # PCI Express Port 21: Ethernet 10G controller + register "PcieRpEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" + end + device pci 1b.5 off end # PCI Express Port 22 + device pci 1b.6 off end # PCI Express Port 23 + device pci 1b.7 off end # PCI Express Port 24 + device pci 1c.0 on # PCI Express Port 1: Aspeed BMC + register "PcieRpEnable[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + end + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + end + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x000C0291" + register "gen3_dec" = "0x000C0c1a" + # TODO aspeed BMC superio, seems to have issues accessing HW bits + # TODO nuvoton superio + end + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + end +end diff --git a/src/mainboard/asrock/e3c246d4i/dsdt.asl b/src/mainboard/asrock/e3c246d4i/dsdt.asl new file mode 100644 index 0000000..97bee96 --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/dsdt.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + +} diff --git a/src/mainboard/asrock/e3c246d4i/gpio.c b/src/mainboard/asrock/e3c246d4i/gpio.c new file mode 100644 index 0000000..186c34c --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/gpio.c @@ -0,0 +1,1208 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - RCIN# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + + /* GPP_A1 - LAD0 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + + /* GPP_A2 - LAD1 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + + /* GPP_A3 - LAD2 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + + /* GPP_A4 - LAD3 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + + /* GPP_A5 - LFRAME# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + + /* GPP_A6 - SERIRQ */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - PIRQA# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + + /* GPP_A8 - CLKRUN# */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - PME# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + + /* GPP_A12 - GPIO */ + /* DW0: 0x80000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, LEVEL, ACPI), + + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + + /* GPP_A14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, ACPI), + + /* GPP_A15 - SUSACK# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + + /* GPP_A16 - CLKOUT_48 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPP_A17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, ACPI), + + /* GPP_A18 - ISH_GP0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - RESERVED */ + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, ACPI), + + /* GPP_A21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_A21, NONE), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_A22, NONE), + + /* GPP_A23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, DEEP, OFF, ACPI), + + /* GPP_B1 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, DEEP, OFF, ACPI), + + /* GPP_B2 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, ACPI), + + /* GPP_B3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, ACPI), + + /* GPP_B4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), + + /* GPP_B5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, ACPI), + + /* GPP_B6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, DEEP, OFF, ACPI), + + /* GPP_B7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, DEEP, OFF, ACPI), + + /* GPP_B8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, ACPI), + + /* GPP_B9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, ACPI), + + /* GPP_B10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), + + /* GPP_B11 - RESERVED */ + + /* GPP_B12 - SLP_S0# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B14, NONE, DEEP, OFF, ACPI), + + /* GPP_B15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), + + /* GPP_B16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, DEEP, OFF, ACPI), + + /* GPP_B17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, DEEP, OFF, ACPI), + + /* GPP_B18 - GSPI0_MOSI */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* GPP_B19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI), + + /* GPP_B20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, DEEP, OFF, ACPI), + + /* GPP_B21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, ACPI), + + /* GPP_B22 - GSPI1_MOSI */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* GPP_B23 - SML1ALERT# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - SMBALERT# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), + + /* GPP_C3 - SML0CLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - SML0ALERT# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), + + /* GPP_C6 - SML1CLK */ + /* DW0: 0x84000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C6, NONE, PLTRST, NF1), + + /* GPP_C7 - SML1DATA */ + /* DW0: 0x84000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C7, NONE, PLTRST, NF1), + + /* GPP_C8 - GPIO */ + /* DW0: 0x84000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, OFF, ACPI), + + /* GPP_C9 - GPIO */ + /* DW0: 0x84000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI), + + /* GPP_C10 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + + /* GPP_C11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, ACPI), + + /* GPP_C12 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, DEEP, OFF, ACPI), + + /* GPP_C13 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, DEEP, OFF, ACPI), + + /* GPP_C14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, DEEP, OFF, ACPI), + + /* GPP_C15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI), + + /* GPP_C16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, DEEP, OFF, ACPI), + + /* GPP_C17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, DEEP, OFF, ACPI), + + /* GPP_C18 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, DEEP, OFF, ACPI), + + /* GPP_C19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, DEEP, OFF, ACPI), + + /* GPP_C20 - RESERVED */ + + /* GPP_C21 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C21, 1, DEEP), + + /* GPP_C22 - GPIO */ + /* DW0: 0x42840102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_SMI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), + + /* GPP_C23 - GPIO */ + /* DW0: 0x40880102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + + /* GPP_D1 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D1, 0, PLTRST), + + /* GPP_D2 - SPI1_MISO */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), + + /* GPP_D3 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, DEEP, OFF, ACPI), + + /* GPP_D4 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D4, NONE, DEEP, OFF, ACPI), + + /* GPP_D5 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D5, 0, DEEP), + + /* GPP_D6 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, ACPI), + + /* GPP_D7 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, ACPI), + + /* GPP_D8 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, ACPI), + + /* GPP_D9 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, OFF, ACPI), + + /* GPP_D10 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, ACPI), + + /* GPP_D11 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, OFF, ACPI), + + /* GPP_D12 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, ACPI), + + /* GPP_D14 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, DEEP, OFF, ACPI), + + /* GPP_D15 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, DEEP, OFF, ACPI), + + /* GPP_D16 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, DEEP, OFF, ACPI), + + /* GPP_D17 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, ACPI), + + /* GPP_D18 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI), + + /* GPP_D19 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI), + + /* GPP_D20 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, ACPI), + + /* GPP_D21 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, DEEP, OFF, ACPI), + + /* GPP_D22 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, ACPI), + + /* GPP_D23 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), + + /* GPP_G1 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G1, NONE, DEEP, OFF, ACPI), + + /* GPP_G2 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G2, NONE, DEEP, OFF, ACPI), + + /* GPP_G3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, DEEP, OFF, ACPI), + + /* GPP_G4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, DEEP, OFF, ACPI), + + /* GPP_G5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G5, NONE, DEEP, OFF, ACPI), + + /* GPP_G6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, DEEP, OFF, ACPI), + + /* GPP_G7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group AZA ------- */ + + /* ------- GPIO Group VGPIO_0 ------- */ + + /* ------- GPIO Group VGPIO_1 ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + + /* GPD1 - ACPRESENT */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + + /* GPD2 - LAN_WAKE# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* GPD3 - PRWBTN# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + + /* GPD4 - SLP_S3# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + + /* GPD5 - SLP_S4# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + + /* GPD6 - SLP_A# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + + /* GPD7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, DEEP, OFF, ACPI), + + /* GPD8 - SUSCLK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + + /* GPD9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPD9, NONE, DEEP, OFF, ACPI), + + /* GPD10 - SLP_S5# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + + /* GPD11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPD11, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_K ------- */ + + /* GPP_K0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, DEEP, OFF, ACPI), + + /* GPP_K1 - GPIO */ + /* DW0: 0x44000101, DW1: 0x00000000 */ + /* DW0: 1 - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, DEEP, OFF, ACPI), + + /* GPP_K2 - GPIO */ + /* DW0: 0x44000101, DW1: 0x00000000 */ + /* DW0: 1 - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, DEEP, OFF, ACPI), + + /* GPP_K3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, DEEP, OFF, ACPI), + + /* GPP_K4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, DEEP, OFF, ACPI), + + /* GPP_K5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, DEEP, OFF, ACPI), + + /* GPP_K6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K6, NONE, DEEP, OFF, ACPI), + + /* GPP_K7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K7, NONE, DEEP, OFF, ACPI), + + /* GPP_K8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K8, NONE, DEEP, OFF, ACPI), + + /* GPP_K9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K9, NONE, DEEP, OFF, ACPI), + + /* GPP_K10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K10, NONE, DEEP, OFF, ACPI), + + /* GPP_K11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, DEEP, OFF, ACPI), + + /* GPP_K12 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_K12, NONE, DEEP, OFF, ACPI), + + /* GPP_K13 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_K13, NONE, DEEP, OFF, ACPI), + + /* GPP_K14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K14, NONE, DEEP, OFF, ACPI), + + /* GPP_K15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, DEEP, OFF, ACPI), + + /* GPP_K16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K16, NONE, DEEP, OFF, ACPI), + + /* GPP_K17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, DEEP, OFF, ACPI), + + /* GPP_K18 - NMI# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_K18, NONE, DEEP, NF1), + + /* GPP_K19 - SMI# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_K19, NONE, DEEP, NF1), + + /* GPP_K20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, DEEP, OFF, ACPI), + + /* GPP_K21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI), + + /* GPP_K22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, DEEP, OFF, ACPI), + + /* GPP_K23 - RESERVED */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, DEEP, OFF, ACPI), + + /* GPP_H1 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, ACPI), + + /* GPP_H2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H2, NONE), + + /* GPP_H3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, ACPI), + + /* GPP_H4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H4, NONE, DEEP, OFF, ACPI), + + /* GPP_H5 - RESERVED */ + + /* GPP_H6 - SRCCLKREQ12# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, DEEP, OFF, ACPI), + + /* GPP_H8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, NONE, DEEP, OFF, ACPI), + + /* GPP_H9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, NONE, DEEP, OFF, ACPI), + + /* GPP_H10 - RESERVED */ + + /* GPP_H11 - RESERVED */ + + /* GPP_H12 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + + /* GPP_H13 - RESERVED */ + + /* GPP_H14 - RESERVED */ + + /* GPP_H15 - GPIO */ + /* DW0: 0x84000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI), + + /* GPP_H16 - SML4CLK */ + /* DW0: 0x84000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H16, NONE, PLTRST, NF1), + + /* GPP_H17 - SML4DATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - SML4ALERT# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + /* DW0: 0x84000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI), + + /* GPP_H20 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + + /* GPP_H21 - GPIO */ + /* DW0: 0x84000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, PLTRST, OFF, ACPI), + + /* GPP_H22 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H22, 1, DEEP), + + /* GPP_H23 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H23, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - SATAXPCIE0 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), + + /* GPP_E1 - SATAXPCIE1 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + + /* GPP_E2 - SATAXPCIE2 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + + /* GPP_E3 - CPU_GP0 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), + + /* GPP_E4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI), + + /* GPP_E5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, ACPI), + + /* GPP_E6 - GPIO */ + /* DW0: 0x80820102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_NMI(GPP_E6, NONE, PLTRST, LEVEL, INVERT), + + /* GPP_E7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + + /* GPP_E8 - SATALED# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* GPP_E9 - USB2_OC0# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + + /* GPP_E10 - USB2_OC1# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + + /* GPP_E11 - USB2_OC2# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + + /* GPP_E12 - USB2_OC3# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - SATAXPCIE3 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - SATAXPCIE4 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + + /* GPP_F2 - SATAXPCIE5 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - SATAXPCIE6 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + + /* GPP_F4 - SATAXPCIE7 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, DEEP, OFF, ACPI), + + /* GPP_F6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, DEEP, OFF, ACPI), + + /* GPP_F7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, DEEP, OFF, ACPI), + + /* GPP_F8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), + + /* GPP_F9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, DEEP, OFF, ACPI), + + /* GPP_F10 - SATA_SCLOCK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + + /* GPP_F11 - SATA_SLOAD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + + /* GPP_F12 - SATA_SDATAOUT1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + + /* GPP_F13 - SATA_SDATAOUT0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + + /* GPP_F14 - PS_ON# */ + /* DW0: 0x44000b00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2), + + /* GPP_F15 - USB2_OC4# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + + /* GPP_F16 - USB2_OC5# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + + /* GPP_F17 - USB2_OC6# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + + /* GPP_F18 - USB2_OC7# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + + /* GPP_F19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, DEEP, OFF, ACPI), + + /* GPP_F20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, DEEP, OFF, ACPI), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, DEEP, OFF, ACPI), + + /* GPP_F22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, DEEP, OFF, ACPI), + + /* GPP_F23 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group CPU ------- */ + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Group GPP_I ------- */ + + /* GPP_I0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, DEEP, OFF, ACPI), + + /* GPP_I1 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_I1, NONE, DEEP, OFF, ACPI), + + /* GPP_I2 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_I2, NONE, DEEP, OFF, ACPI), + + /* GPP_I3 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_I3, NONE, DEEP, OFF, ACPI), + + /* GPP_I4 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, DEEP, OFF, ACPI), + + /* GPP_I5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I5, NONE, DEEP, OFF, ACPI), + + /* GPP_I6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I6, NONE, DEEP, OFF, ACPI), + + /* GPP_I7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, DEEP, OFF, ACPI), + + /* GPP_I8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I8, NONE, DEEP, OFF, ACPI), + + /* GPP_I9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, DEEP, OFF, ACPI), + + /* GPP_I10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, DEEP, OFF, ACPI), + + /* GPP_I11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I11, NONE, DEEP, OFF, ACPI), + + /* GPP_I12 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I12, NONE, DEEP, OFF, ACPI), + + /* GPP_I13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I13, NONE, DEEP, OFF, ACPI), + + /* GPP_I14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_I14, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_J ------- */ + + /* GPP_J0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, DEEP, OFF, ACPI), + + /* GPP_J1 - CPU_C10_GATE# */ + /* DW0: 0x44000a01, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1 - IGNORED */ + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2), + + /* GPP_J2 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J2, NONE, DEEP, OFF, ACPI), + + /* GPP_J3 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J3, NONE, DEEP, OFF, ACPI), + + /* GPP_J4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_J4, NONE, DEEP, OFF, ACPI), + + /* GPP_J5 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J5, NONE, DEEP, OFF, ACPI), + + /* GPP_J6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, DEEP, OFF, ACPI), + + /* GPP_J7 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, DEEP, OFF, ACPI), + + /* GPP_J8 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J8, NONE, DEEP, OFF, ACPI), + + /* GPP_J9 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J9, NONE, DEEP, OFF, ACPI), + + /* GPP_J10 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, DEEP, OFF, ACPI), + + /* GPP_J11 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, DEEP, OFF, ACPI), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct pad_config early_gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - RCIN# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + + /* GPP_A1 - LAD0 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + + /* GPP_A2 - LAD1 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + + /* GPP_A3 - LAD2 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + + /* GPP_A4 - LAD3 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + + /* GPP_A5 - LFRAME# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + + /* GPP_A6 - SERIRQ */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - PIRQA# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + + /* GPP_A8 - CLKRUN# */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - PME# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + + /* GPP_A12 - GPIO */ + /* DW0: 0x80000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, LEVEL, ACPI), + + /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + + /* GPP_A14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, ACPI), + + /* GPP_A15 - SUSACK# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h b/src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h new file mode 100644 index 0000000..c6393be --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/asrock/e3c246d4i/ramstage.c b/src/mainboard/asrock/e3c246d4i/ramstage.c new file mode 100644 index 0000000..43ee54f --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <mainboard/gpio.h> + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/asrock/e3c246d4i/romstage.c b/src/mainboard/asrock/e3c246d4i/romstage.c new file mode 100644 index 0000000..3133a5a --- /dev/null +++ b/src/mainboard/asrock/e3c246d4i/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + /* Just for esthetic reasons the spd indices are set up like on + the hardware starting from closest to the cpu. */ + .spd[1] = + { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa2}, + }, + .spd[0] = + { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[3] = + { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa8}, + }, + .spd[2] = + { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .rcomp_resistor = {121, 75, 100}, + .rcomp_targets = {50, 26, 20, 20, 26}, + .dq_pins_interleaved = 1, + .ect = 0, + .vref_ca_config = 2, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS
by EricR Lai (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Subrata Banik, Arthur Heymans, Morgan Jang, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56332 ) Change subject: soc/intel/xeon_sp/cpx: Align Cooper Lake CPUID as per EDS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I240a06e3b3d7e3dc080f9a9ed1539fadc982495d Gerrit-Change-Number: 56332 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 12:02:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2021