coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by Marshall Dawson (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Julian Schroeder. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56188 ) Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56188/comment/209e57b2_8bd2a9f1 PS6, Line 11: Can you add two lines (plus another blank line) BUG=b:185814875 TEST=<whatever you did> -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 6 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:10:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Enable south XHCI ports 1 and 2
by Tim Wawrzynczak (Code Review) 15 Jul '21

15 Jul '21

Tim Wawrzynczak has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/52088 ) Change subject: mb/google/brya: Enable south XHCI ports 1 and 2 ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/52088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637 Gerrit-Change-Number: 52088 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

1 0

Change in coreboot[master]: Revert "mb/google/brya: Enable south XHCI ports 1 and 2"
by Tim Wawrzynczak (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Ronak Kanabar, Subrata Banik, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, EricR Lai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56132 to review the following change. Change subject: Revert "mb/google/brya: Enable south XHCI ports 1 and 2" ...................................................................... Revert "mb/google/brya: Enable south XHCI ports 1 and 2" This reverts commit f7f715dff38c4a629139b2493ed6e0d7cc2eb36f. Reason for revert: FSP 2207.01 uses the UsbTcPortEn UPD for TCSS XHCI enable Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56132/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index d7e2522..3155d04 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -39,12 +39,6 @@ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 - # TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081 - # uses port enable for south XHCI ports to determine if TCSS - # ports should be enabled. Until FSP is fixed, enable south - # XHCI ports 1 and 2. - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "SerialIoI2cMode" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/56132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Gerrit-Change-Number: 56132 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/alderlake: Add virtual GPIOs for community 1
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55270 ) Change subject: soc/intel/alderlake: Add virtual GPIOs for community 1 ...................................................................... soc/intel/alderlake: Add virtual GPIOs for community 1 Alder Lake SoC has virtual GPIOs for community 1 which was being programmed by FSP and hence was skipped by coreboot. As part of moving most of the GPIO programming to coreboot, we're skipping this programming in FSP now. TEST=Check register offset to see if programming is correct. Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h 2 files changed, 281 insertions(+), 223 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index 6d9e184..f845def 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -50,6 +50,8 @@ INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 160), /* GPP_D */ + INTEL_GPP(GPP_S0, GPP_CPU_RSVD_1, GPP_CPU_RSVD_24), /* GPP_CPU_RSVD */ + INTEL_GPP(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_37), /* vGPIO */ }; static const struct vw_entries adl_community1_vw[] = { @@ -64,8 +66,9 @@ /* This community is not visible to the OS */ static const struct pad_group adl_community3_groups[] = { - INTEL_GPP(GPP_CPU_RSVD_1, GPP_CPU_RSVD_1, GPP_vGPIO_PCIE_83), /* vGPIO */ + INTEL_GPP(GPP_CPU_RSVD_25, GPP_CPU_RSVD_25, GPP_vGPIO_PCIE_83), /* vGPIO_PCIE */ }; + static const struct pad_group adl_community4_groups[] = { INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */ INTEL_GPP_BASE(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK, 288), /* GPP_F */ diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h index b1f2341..9a0a3f4 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -169,257 +169,312 @@ #define GPP_D19 118 #define GPP_GSPI2_CLK_LOOPBK 119 +/* Reserved GPIOs */ +#define GPP_CPU_RSVD_1 120 +#define GPP_CPU_RSVD_2 121 +#define GPP_CPU_RSVD_3 122 +#define GPP_CPU_RSVD_4 123 +#define GPP_CPU_RSVD_5 124 +#define GPP_CPU_RSVD_6 125 +#define GPP_CPU_RSVD_7 126 +#define GPP_CPU_RSVD_8 127 +#define GPP_CPU_RSVD_9 128 +#define GPP_CPU_RSVD_10 129 +#define GPP_CPU_RSVD_11 130 +#define GPP_CPU_RSVD_12 131 +#define GPP_CPU_RSVD_13 132 +#define GPP_CPU_RSVD_14 133 +#define GPP_CPU_RSVD_15 134 +#define GPP_CPU_RSVD_16 135 +#define GPP_CPU_RSVD_17 136 +#define GPP_CPU_RSVD_18 137 +#define GPP_CPU_RSVD_19 138 +#define GPP_CPU_RSVD_20 139 +#define GPP_CPU_RSVD_21 140 +#define GPP_CPU_RSVD_22 141 +#define GPP_CPU_RSVD_23 142 +#define GPP_CPU_RSVD_24 143 + +/* Group VGPIO */ +#define GPP_VGPIO_0 144 +#define GPP_VGPIO_4 145 +#define GPP_VGPIO_5 146 +#define GPP_VGPIO_6 147 +#define GPP_VGPIO_7 148 +#define GPP_VGPIO_8 149 +#define GPP_VGPIO_9 150 +#define GPP_VGPIO_10 151 +#define GPP_VGPIO_11 152 +#define GPP_VGPIO_12 153 +#define GPP_VGPIO_13 154 +#define GPP_VGPIO_18 155 +#define GPP_VGPIO_19 156 +#define GPP_VGPIO_20 157 +#define GPP_VGPIO_21 158 +#define GPP_VGPIO_22 159 +#define GPP_VGPIO_23 160 +#define GPP_VGPIO_24 161 +#define GPP_VGPIO_25 162 +#define GPP_VGPIO_30 163 +#define GPP_VGPIO_31 164 +#define GPP_VGPIO_32 165 +#define GPP_VGPIO_33 166 +#define GPP_VGPIO_34 167 +#define GPP_VGPIO_35 168 +#define GPP_VGPIO_36 169 +#define GPP_VGPIO_37 170 + #define GPIO_COM1_START GPP_S0 -#define GPIO_COM1_END GPP_GSPI2_CLK_LOOPBK +#define GPIO_COM1_END GPP_VGPIO_37 #define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) /* Group GPD */ -#define GPD0 120 -#define GPD1 121 -#define GPD2 122 -#define GPD3 123 -#define GPD4 124 -#define GPD5 125 -#define GPD6 126 -#define GPD7 127 -#define GPD8 128 -#define GPD9 129 -#define GPD10 130 -#define GPD11 131 -#define GPD_INPUT3VSEL 132 -#define GPD_SLP_LANB 133 -#define GPD_SLP_SUSB 134 -#define GPD_WAKEB 135 -#define GPD_DRAM_RESETB 136 +#define GPD0 171 +#define GPD1 172 +#define GPD2 173 +#define GPD3 174 +#define GPD4 175 +#define GPD5 176 +#define GPD6 177 +#define GPD7 178 +#define GPD8 179 +#define GPD9 180 +#define GPD10 181 +#define GPD11 182 +#define GPD_INPUT3VSEL 183 +#define GPD_SLP_LANB 184 +#define GPD_SLP_SUSB 185 +#define GPD_WAKEB 186 +#define GPD_DRAM_RESETB 187 #define GPIO_COM2_START GPD0 #define GPIO_COM2_END GPD_DRAM_RESETB #define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) /* PCIE VGPIO group */ -#define GPP_CPU_RSVD_1 137 -#define GPP_CPU_RSVD_2 138 -#define GPP_CPU_RSVD_3 139 -#define GPP_CPU_RSVD_4 140 -#define GPP_CPU_RSVD_5 141 -#define GPP_CPU_RSVD_6 142 -#define GPP_CPU_RSVD_7 143 -#define GPP_CPU_RSVD_8 144 -#define GPP_CPU_RSVD_9 145 -#define GPP_CPU_RSVD_10 146 -#define GPP_CPU_RSVD_11 147 -#define GPP_CPU_RSVD_12 148 -#define GPP_CPU_RSVD_13 149 -#define GPP_CPU_RSVD_14 150 -#define GPP_CPU_RSVD_15 151 -#define GPP_vGPIO_PCIE_0 152 -#define GPP_vGPIO_PCIE_1 153 -#define GPP_vGPIO_PCIE_2 154 -#define GPP_vGPIO_PCIE_3 155 -#define GPP_vGPIO_PCIE_4 156 -#define GPP_vGPIO_PCIE_5 157 -#define GPP_vGPIO_PCIE_6 158 -#define GPP_vGPIO_PCIE_7 159 -#define GPP_vGPIO_PCIE_8 160 -#define GPP_vGPIO_PCIE_9 161 -#define GPP_vGPIO_PCIE_10 162 -#define GPP_vGPIO_PCIE_11 163 -#define GPP_vGPIO_PCIE_12 164 -#define GPP_vGPIO_PCIE_13 165 -#define GPP_vGPIO_PCIE_14 166 -#define GPP_vGPIO_PCIE_15 167 -#define GPP_vGPIO_PCIE_16 168 -#define GPP_vGPIO_PCIE_17 169 -#define GPP_vGPIO_PCIE_18 170 -#define GPP_vGPIO_PCIE_19 171 -#define GPP_vGPIO_PCIE_20 172 -#define GPP_vGPIO_PCIE_21 173 -#define GPP_vGPIO_PCIE_22 174 -#define GPP_vGPIO_PCIE_23 175 -#define GPP_vGPIO_PCIE_24 176 -#define GPP_vGPIO_PCIE_25 177 -#define GPP_vGPIO_PCIE_26 178 -#define GPP_vGPIO_PCIE_27 179 -#define GPP_vGPIO_PCIE_28 180 -#define GPP_vGPIO_PCIE_29 181 -#define GPP_vGPIO_PCIE_30 182 -#define GPP_vGPIO_PCIE_31 183 -#define GPP_vGPIO_PCIE_32 184 -#define GPP_vGPIO_PCIE_33 185 -#define GPP_vGPIO_PCIE_34 186 -#define GPP_vGPIO_PCIE_35 187 -#define GPP_vGPIO_PCIE_36 188 -#define GPP_vGPIO_PCIE_37 189 -#define GPP_vGPIO_PCIE_38 190 -#define GPP_vGPIO_PCIE_39 191 -#define GPP_vGPIO_PCIE_40 192 -#define GPP_vGPIO_PCIE_41 193 -#define GPP_vGPIO_PCIE_42 194 -#define GPP_vGPIO_PCIE_43 195 -#define GPP_vGPIO_PCIE_44 196 -#define GPP_vGPIO_PCIE_45 197 -#define GPP_vGPIO_PCIE_46 198 -#define GPP_vGPIO_PCIE_47 199 -#define GPP_vGPIO_PCIE_48 200 -#define GPP_vGPIO_PCIE_49 201 -#define GPP_vGPIO_PCIE_50 202 -#define GPP_vGPIO_PCIE_51 203 -#define GPP_vGPIO_PCIE_52 204 -#define GPP_vGPIO_PCIE_53 205 -#define GPP_vGPIO_PCIE_54 206 -#define GPP_vGPIO_PCIE_55 207 -#define GPP_vGPIO_PCIE_56 208 -#define GPP_vGPIO_PCIE_57 209 -#define GPP_vGPIO_PCIE_58 210 -#define GPP_vGPIO_PCIE_59 211 -#define GPP_vGPIO_PCIE_60 212 -#define GPP_vGPIO_PCIE_61 213 -#define GPP_vGPIO_PCIE_62 214 -#define GPP_vGPIO_PCIE_63 215 -#define GPP_vGPIO_PCIE_64 216 -#define GPP_vGPIO_PCIE_65 217 -#define GPP_vGPIO_PCIE_66 218 -#define GPP_vGPIO_PCIE_67 219 -#define GPP_vGPIO_PCIE_68 220 -#define GPP_vGPIO_PCIE_69 221 -#define GPP_vGPIO_PCIE_70 222 -#define GPP_vGPIO_PCIE_71 223 -#define GPP_vGPIO_PCIE_72 224 -#define GPP_vGPIO_PCIE_73 225 -#define GPP_vGPIO_PCIE_74 226 -#define GPP_vGPIO_PCIE_75 227 -#define GPP_vGPIO_PCIE_76 228 -#define GPP_vGPIO_PCIE_77 229 -#define GPP_vGPIO_PCIE_78 230 -#define GPP_vGPIO_PCIE_79 231 -#define GPP_CPU_RSVD_16 232 -#define GPP_CPU_RSVD_17 233 -#define GPP_CPU_RSVD_18 234 -#define GPP_CPU_RSVD_19 235 -#define GPP_CPU_RSVD_20 236 -#define GPP_CPU_RSVD_21 237 -#define GPP_CPU_RSVD_22 238 -#define GPP_CPU_RSVD_23 239 -#define GPP_vGPIO_PCIE_80 240 -#define GPP_vGPIO_PCIE_81 241 -#define GPP_vGPIO_PCIE_82 242 -#define GPP_vGPIO_PCIE_83 243 +#define GPP_CPU_RSVD_25 188 +#define GPP_CPU_RSVD_26 189 +#define GPP_CPU_RSVD_27 190 +#define GPP_CPU_RSVD_28 191 +#define GPP_CPU_RSVD_29 192 +#define GPP_CPU_RSVD_30 193 +#define GPP_CPU_RSVD_31 194 +#define GPP_CPU_RSVD_32 195 +#define GPP_CPU_RSVD_33 196 +#define GPP_CPU_RSVD_34 197 +#define GPP_CPU_RSVD_35 198 +#define GPP_CPU_RSVD_36 199 +#define GPP_CPU_RSVD_37 200 +#define GPP_CPU_RSVD_38 201 +#define GPP_CPU_RSVD_39 202 +#define GPP_vGPIO_PCIE_0 203 +#define GPP_vGPIO_PCIE_1 204 +#define GPP_vGPIO_PCIE_2 205 +#define GPP_vGPIO_PCIE_3 206 +#define GPP_vGPIO_PCIE_4 207 +#define GPP_vGPIO_PCIE_5 208 +#define GPP_vGPIO_PCIE_6 209 +#define GPP_vGPIO_PCIE_7 210 +#define GPP_vGPIO_PCIE_8 211 +#define GPP_vGPIO_PCIE_9 212 +#define GPP_vGPIO_PCIE_10 213 +#define GPP_vGPIO_PCIE_11 214 +#define GPP_vGPIO_PCIE_12 215 +#define GPP_vGPIO_PCIE_13 216 +#define GPP_vGPIO_PCIE_14 217 +#define GPP_vGPIO_PCIE_15 218 +#define GPP_vGPIO_PCIE_16 219 +#define GPP_vGPIO_PCIE_17 220 +#define GPP_vGPIO_PCIE_18 221 +#define GPP_vGPIO_PCIE_19 222 +#define GPP_vGPIO_PCIE_20 223 +#define GPP_vGPIO_PCIE_21 224 +#define GPP_vGPIO_PCIE_22 225 +#define GPP_vGPIO_PCIE_23 226 +#define GPP_vGPIO_PCIE_24 227 +#define GPP_vGPIO_PCIE_25 228 +#define GPP_vGPIO_PCIE_26 229 +#define GPP_vGPIO_PCIE_27 230 +#define GPP_vGPIO_PCIE_28 231 +#define GPP_vGPIO_PCIE_29 232 +#define GPP_vGPIO_PCIE_30 233 +#define GPP_vGPIO_PCIE_31 234 +#define GPP_vGPIO_PCIE_32 235 +#define GPP_vGPIO_PCIE_33 236 +#define GPP_vGPIO_PCIE_34 237 +#define GPP_vGPIO_PCIE_35 238 +#define GPP_vGPIO_PCIE_36 239 +#define GPP_vGPIO_PCIE_37 240 +#define GPP_vGPIO_PCIE_38 241 +#define GPP_vGPIO_PCIE_39 242 +#define GPP_vGPIO_PCIE_40 243 +#define GPP_vGPIO_PCIE_41 244 +#define GPP_vGPIO_PCIE_42 245 +#define GPP_vGPIO_PCIE_43 246 +#define GPP_vGPIO_PCIE_44 247 +#define GPP_vGPIO_PCIE_45 248 +#define GPP_vGPIO_PCIE_46 249 +#define GPP_vGPIO_PCIE_47 250 +#define GPP_vGPIO_PCIE_48 251 +#define GPP_vGPIO_PCIE_49 252 +#define GPP_vGPIO_PCIE_50 253 +#define GPP_vGPIO_PCIE_51 254 +#define GPP_vGPIO_PCIE_52 255 +#define GPP_vGPIO_PCIE_53 256 +#define GPP_vGPIO_PCIE_54 257 +#define GPP_vGPIO_PCIE_55 258 +#define GPP_vGPIO_PCIE_56 259 +#define GPP_vGPIO_PCIE_57 260 +#define GPP_vGPIO_PCIE_58 261 +#define GPP_vGPIO_PCIE_59 262 +#define GPP_vGPIO_PCIE_60 263 +#define GPP_vGPIO_PCIE_61 264 +#define GPP_vGPIO_PCIE_62 265 +#define GPP_vGPIO_PCIE_63 266 +#define GPP_vGPIO_PCIE_64 267 +#define GPP_vGPIO_PCIE_65 268 +#define GPP_vGPIO_PCIE_66 269 +#define GPP_vGPIO_PCIE_67 270 +#define GPP_vGPIO_PCIE_68 271 +#define GPP_vGPIO_PCIE_69 272 +#define GPP_vGPIO_PCIE_70 273 +#define GPP_vGPIO_PCIE_71 274 +#define GPP_vGPIO_PCIE_72 275 +#define GPP_vGPIO_PCIE_73 276 +#define GPP_vGPIO_PCIE_74 277 +#define GPP_vGPIO_PCIE_75 278 +#define GPP_vGPIO_PCIE_76 279 +#define GPP_vGPIO_PCIE_77 280 +#define GPP_vGPIO_PCIE_78 281 +#define GPP_vGPIO_PCIE_79 282 +#define GPP_CPU_RSVD_40 283 +#define GPP_CPU_RSVD_41 284 +#define GPP_CPU_RSVD_42 285 +#define GPP_CPU_RSVD_43 286 +#define GPP_CPU_RSVD_44 287 +#define GPP_CPU_RSVD_45 288 +#define GPP_CPU_RSVD_46 289 +#define GPP_CPU_RSVD_47 290 +#define GPP_vGPIO_PCIE_80 291 +#define GPP_vGPIO_PCIE_81 292 +#define GPP_vGPIO_PCIE_82 293 +#define GPP_vGPIO_PCIE_83 294 -#define GPIO_COM3_START GPP_CPU_RSVD_1 +#define GPIO_COM3_START GPP_CPU_RSVD_25 #define GPIO_COM3_END GPP_vGPIO_PCIE_83 #define NUM_GPIO_COM3_PADS (GPIO_COM3_END - GPIO_COM3_START + 1) /* Group C */ -#define GPP_C0 244 -#define GPP_C1 245 -#define GPP_C2 246 -#define GPP_C3 247 -#define GPP_C4 248 -#define GPP_C5 249 -#define GPP_C6 250 -#define GPP_C7 251 -#define GPP_C8 252 -#define GPP_C9 253 -#define GPP_C10 254 -#define GPP_C11 255 -#define GPP_C12 256 -#define GPP_C13 257 -#define GPP_C14 258 -#define GPP_C15 259 -#define GPP_C16 260 -#define GPP_C17 261 -#define GPP_C18 262 -#define GPP_C19 263 -#define GPP_C20 264 -#define GPP_C21 265 -#define GPP_C22 266 -#define GPP_C23 267 +#define GPP_C0 295 +#define GPP_C1 296 +#define GPP_C2 297 +#define GPP_C3 298 +#define GPP_C4 299 +#define GPP_C5 300 +#define GPP_C6 301 +#define GPP_C7 302 +#define GPP_C8 303 +#define GPP_C9 304 +#define GPP_C10 305 +#define GPP_C11 306 +#define GPP_C12 307 +#define GPP_C13 308 +#define GPP_C14 309 +#define GPP_C15 310 +#define GPP_C16 311 +#define GPP_C17 312 +#define GPP_C18 313 +#define GPP_C19 314 +#define GPP_C20 315 +#define GPP_C21 316 +#define GPP_C22 317 +#define GPP_C23 318 /* Group F */ -#define GPP_F0 268 -#define GPP_F1 269 -#define GPP_F2 270 -#define GPP_F3 271 -#define GPP_F4 272 -#define GPP_F5 273 -#define GPP_F6 274 -#define GPP_F7 275 -#define GPP_F8 276 -#define GPP_F9 277 -#define GPP_F10 278 -#define GPP_F11 279 -#define GPP_F12 280 -#define GPP_F13 281 -#define GPP_F14 282 -#define GPP_F15 283 -#define GPP_F16 284 -#define GPP_F17 285 -#define GPP_F18 286 -#define GPP_F19 287 -#define GPP_F20 288 -#define GPP_F21 289 -#define GPP_F22 290 -#define GPP_F23 291 -#define GPP_F_CLK_LOOPBK 292 +#define GPP_F0 319 +#define GPP_F1 320 +#define GPP_F2 321 +#define GPP_F3 322 +#define GPP_F4 323 +#define GPP_F5 324 +#define GPP_F6 325 +#define GPP_F7 326 +#define GPP_F8 327 +#define GPP_F9 328 +#define GPP_F10 329 +#define GPP_F11 330 +#define GPP_F12 331 +#define GPP_F13 332 +#define GPP_F14 333 +#define GPP_F15 334 +#define GPP_F16 335 +#define GPP_F17 336 +#define GPP_F18 337 +#define GPP_F19 338 +#define GPP_F20 339 +#define GPP_F21 340 +#define GPP_F22 341 +#define GPP_F23 342 +#define GPP_F_CLK_LOOPBK 343 /* Group HVMOS */ -#define GPP_L_BKLTEN 293 -#define GPP_L_BKLTCTL 294 -#define GPP_L_VDDEN 295 -#define GPP_SYS_PWROK 296 -#define GPP_SYS_RESETB 297 -#define GPP_MLK_RSTB 298 +#define GPP_L_BKLTEN 344 +#define GPP_L_BKLTCTL 345 +#define GPP_L_VDDEN 346 +#define GPP_SYS_PWROK 347 +#define GPP_SYS_RESETB 348 +#define GPP_MLK_RSTB 349 /* Group E */ -#define GPP_E0 299 -#define GPP_E1 300 -#define GPP_E2 301 -#define GPP_E3 302 -#define GPP_E4 303 -#define GPP_E5 304 -#define GPP_E6 305 -#define GPP_E7 306 -#define GPP_E8 307 -#define GPP_E9 308 -#define GPP_E10 309 -#define GPP_E11 310 -#define GPP_E12 311 -#define GPP_E13 312 -#define GPP_E14 313 -#define GPP_E15 314 -#define GPP_E16 315 -#define GPP_E17 316 -#define GPP_E18 317 -#define GPP_E19 318 -#define GPP_E20 319 -#define GPP_E21 320 -#define GPP_E22 321 -#define GPP_E23 322 -#define GPP_E_CLK_LOOPBK 323 +#define GPP_E0 350 +#define GPP_E1 351 +#define GPP_E2 352 +#define GPP_E3 353 +#define GPP_E4 354 +#define GPP_E5 355 +#define GPP_E6 356 +#define GPP_E7 357 +#define GPP_E8 358 +#define GPP_E9 359 +#define GPP_E10 360 +#define GPP_E11 361 +#define GPP_E12 362 +#define GPP_E13 363 +#define GPP_E14 364 +#define GPP_E15 365 +#define GPP_E16 366 +#define GPP_E17 367 +#define GPP_E18 368 +#define GPP_E19 369 +#define GPP_E20 370 +#define GPP_E21 371 +#define GPP_E22 372 +#define GPP_E23 373 +#define GPP_E_CLK_LOOPBK 374 #define GPIO_COM4_START GPP_C0 #define GPIO_COM4_END GPP_E_CLK_LOOPBK #define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) /* Group R */ -#define GPP_R0 324 -#define GPP_R1 325 -#define GPP_R2 326 -#define GPP_R3 327 -#define GPP_R4 328 -#define GPP_R5 329 -#define GPP_R6 330 -#define GPP_R7 331 +#define GPP_R0 375 +#define GPP_R1 376 +#define GPP_R2 377 +#define GPP_R3 378 +#define GPP_R4 379 +#define GPP_R5 380 +#define GPP_R6 381 +#define GPP_R7 382 /* Group SPI0 */ -#define GPP_SPI0_IO_2 332 -#define GPP_SPI0_IO_3 333 -#define GPP_SPI0_MOSI_IO_0 334 -#define GPP_SPI0_MOSI_IO_1 335 -#define GPP_SPI0_TPM_CSB 336 -#define GPP_SPI0_FLASH_0_CSB 337 -#define GPP_SPI0_FLASH_1_CSB 338 -#define GPP_SPI0_CLK 339 +#define GPP_SPI0_IO_2 383 +#define GPP_SPI0_IO_3 384 +#define GPP_SPI0_MOSI_IO_0 385 +#define GPP_SPI0_MOSI_IO_1 386 +#define GPP_SPI0_TPM_CSB 387 +#define GPP_SPI0_FLASH_0_CSB 388 +#define GPP_SPI0_FLASH_1_CSB 389 +#define GPP_SPI0_CLK 390 #define GPIO_COM5_START GPP_R0 #define GPIO_COM5_END GPP_SPI0_CLK -- To view, visit https://review.coreboot.org/c/coreboot/+/55270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf Gerrit-Change-Number: 55270 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/pc80/rtc: Make use of alt-century byte configurable
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Nico Huber, Werner Zeh. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56214 ) Change subject: drivers/pc80/rtc: Make use of alt-century byte configurable ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Werner, I remember that you had some trouble with the RTC piece, so what's your opinion on this? -- To view, visit https://review.coreboot.org/c/coreboot/+/56214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893 Gerrit-Change-Number: 56214 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:07:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers: spi_flash: Add Fast Read Dual I/O support
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56287 ) Change subject: drivers: spi_flash: Add Fast Read Dual I/O support ...................................................................... drivers: spi_flash: Add Fast Read Dual I/O support The Fast Read Dual Output and Fast Read Dual I/O commands are practically identical, the only difference being how the read address is transferred (saving a whooping 2 bytes which is totally irrelevant for the amounts of data coreboot tends to read). We originally implemented Fast Read Dual Output since it's the older command and some older Winbond chips only supported that one... but it seems that some older Macronix parts for whatever reason chose to only support Fast Read Dual I/O instead. So in order to make this work for as many parts as possible, I guess we'll have to implement both. (Also, the Macronix device ID situation is utter madness with different chips with different capabilities often having the same ID, so we basically have to make a best-effort guess to strike a trade-off between fast speeds and best chance at supporting all chips. If this turns out to be a problem later, we may have to add Kconfig overrides for this or resort to SFDP parsing, although that would defeat the whole point of trying to be fast.) BUG=b:193486682 TEST=Booted CoachZ (with Dual I/O) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h M src/drivers/spi/winbond.c M src/include/spi_flash.h 6 files changed, 100 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 15ad907..fc2a405 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -31,72 +31,84 @@ .id[0] = 0x4014, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, /* also GD25Q80B */ { /* GD25Q16 */ .id[0] = 0x4015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, /* also GD25Q16B */ { /* GD25Q32B */ .id[0] = 0x4016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, /* also GD25Q32B */ { /* GD25Q64 */ .id[0] = 0x4017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, /* also GD25Q64B, GD25B64C */ { /* GD25Q128 */ .id[0] = 0x4018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, /* also GD25Q128B */ { /* GD25VQ80C */ .id[0] = 0x4214, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, { /* GD25VQ16C */ .id[0] = 0x4215, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, { /* GD25LQ80 */ .id[0] = 0x6014, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, { /* GD25LQ16 */ .id[0] = 0x6015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, { /* GD25LQ32 */ .id[0] = 0x6016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, { /* GD25LQ64C */ .id[0] = 0x6017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, /* also GD25LB64C */ { /* GD25LQ128 */ .id[0] = 0x6018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, }; diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 69e7a9f..b6981e0 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -63,55 +63,75 @@ .id[0] = 0x2415, .nr_sectors_shift = 9, }, + /* + * NOTE: C225xx JEDEC IDs are basically useless because Macronix keeps + * reusing the same IDs for vastly different chips. 35E versions always + * seem to support Dual I/O but not Dual Output, while 35F versions seem + * to support both, so we only set Dual I/O here to improve our chances + * of compatibility. Since Macronix makes it impossible to search all + * different parts that it recklessly assigned the same IDs to, it's + * hard to know if there may be parts that don't even support Dual I/O + * with these IDs, though (or what we should do if there are). + */ { /* MX25L1635E */ .id[0] = 0x2515, .nr_sectors_shift = 9, + .fast_read_dual_io_support = 1, }, { /* MX25U8032E */ .id[0] = 0x2534, .nr_sectors_shift = 8, + .fast_read_dual_io_support = 1, }, { - /* MX25U1635E */ + /* MX25U1635E/MX25U1635F */ .id[0] = 0x2535, .nr_sectors_shift = 9, + .fast_read_dual_io_support = 1, }, { - /* MX25U3235E */ + /* MX25U3235E/MX25U3235F */ .id[0] = 0x2536, .nr_sectors_shift = 10, + .fast_read_dual_io_support = 1, }, { - /* MX25U6435F */ + /* MX25U6435E/MX25U6435F */ .id[0] = 0x2537, .nr_sectors_shift = 11, + .fast_read_dual_io_support = 1, }, { /* MX25U12835F */ .id[0] = 0x2538, .nr_sectors_shift = 12, + .fast_read_dual_io_support = 1, }, { /* MX25U25635F */ .id[0] = 0x2539, .nr_sectors_shift = 13, + .fast_read_dual_io_support = 1, }, { - /* MX25U51245G */ + /* MX25U51235F */ .id[0] = 0x253a, .nr_sectors_shift = 14, + .fast_read_dual_io_support = 1, }, { /* MX25L12855E */ .id[0] = 0x2618, .nr_sectors_shift = 12, + .fast_read_dual_io_support = 1, }, { /* MX25L3235D/MX25L3225D/MX25L3236D/MX25L3237D */ .id[0] = 0x5e16, .nr_sectors_shift = 10, + .fast_read_dual_io_support = 1, }, { /* MX25L6495F */ diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index b674749..f3cecd5 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -20,7 +20,7 @@ cmd[3] = addr >> 0; } -static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, +static int do_spi_flash_cmd(const struct spi_slave *spi, const u8 *dout, size_t bytes_out, void *din, size_t bytes_in) { int ret; @@ -51,8 +51,8 @@ return ret; } -static int do_dual_read_cmd(const struct spi_slave *spi, const void *dout, - size_t bytes_out, void *din, size_t bytes_in) +static int do_dual_output_cmd(const struct spi_slave *spi, const u8 *dout, + size_t bytes_out, void *din, size_t bytes_in) { int ret; @@ -79,6 +79,31 @@ return ret; } +static int do_dual_io_cmd(const struct spi_slave *spi, const u8 *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + int ret; + + /* Only the very first byte (opcode) is transferred in "single" mode. */ + struct spi_op vector = { .dout = dout, .bytesout = 1, + .din = NULL, .bytesin = 0 }; + + ret = spi_claim_bus(spi); + if (ret) + return ret; + + ret = spi_xfer_vector(spi, &vector, 1); + + if (!ret) + ret = spi->ctrlr->xfer_dual(spi, &dout[1], bytes_out - 1, NULL, 0); + + if (!ret) + ret = spi->ctrlr->xfer_dual(spi, NULL, 0, din, bytes_in); + + spi_release_bus(spi); + return ret; +} + int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len) { int ret = do_spi_flash_cmd(spi, &cmd, sizeof(cmd), response, len); @@ -119,18 +144,23 @@ { u8 cmd[5]; int ret, cmd_len; - int (*do_cmd)(const struct spi_slave *spi, const void *din, + int (*do_cmd)(const struct spi_slave *spi, const u8 *din, size_t in_bytes, void *out, size_t out_bytes); if (CONFIG(SPI_FLASH_NO_FAST_READ)) { cmd_len = 4; cmd[0] = CMD_READ_ARRAY_SLOW; do_cmd = do_spi_flash_cmd; - } else if (flash->flags.dual_spi && flash->spi.ctrlr->xfer_dual) { + } else if (flash->flags.dual_io && flash->spi.ctrlr->xfer_dual) { + cmd_len = 5; + cmd[0] = CMD_READ_FAST_DUAL_IO; + cmd[4] = 0; + do_cmd = do_dual_io_cmd; + } else if (flash->flags.dual_output && flash->spi.ctrlr->xfer_dual) { cmd_len = 5; cmd[0] = CMD_READ_FAST_DUAL_OUTPUT; cmd[4] = 0; - do_cmd = do_dual_read_cmd; + do_cmd = do_dual_output_cmd; } else { cmd_len = 5; cmd[0] = CMD_READ_ARRAY_FAST; @@ -352,7 +382,8 @@ flash->pp_cmd = vi->desc->pp_cmd; flash->wren_cmd = vi->desc->wren_cmd; - flash->flags.dual_spi = part->fast_read_dual_output_support; + flash->flags.dual_output = part->fast_read_dual_output_support; + flash->flags.dual_io = part->fast_read_dual_io_support; flash->ops = &vi->desc->ops; flash->prot_ops = vi->prot_ops; @@ -471,8 +502,10 @@ } const char *mode_string = ""; - if (flash->flags.dual_spi && spi.ctrlr->xfer_dual) - mode_string = " (Dual SPI mode)"; + if (flash->flags.dual_io && spi.ctrlr->xfer_dual) + mode_string = " (Dual I/O mode)"; + else if (flash->flags.dual_output && spi.ctrlr->xfer_dual) + mode_string = " (Dual Output mode)"; printk(BIOS_INFO, "SF: Detected %02x %04x with sector size 0x%x, total 0x%x%s\n", flash->vendor, flash->model, flash->sector_size, flash->size, mode_string); diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index b4d39b3..4a7beea 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -15,6 +15,7 @@ #define CMD_READ_ARRAY_LEGACY 0xe8 #define CMD_READ_FAST_DUAL_OUTPUT 0x3b +#define CMD_READ_FAST_DUAL_IO 0xbb #define CMD_READ_STATUS 0x05 #define CMD_WRITE_ENABLE 0x06 @@ -69,8 +70,9 @@ uint16_t id[2]; /* Log based 2 total number of sectors. */ uint16_t nr_sectors_shift: 4; - uint16_t fast_read_dual_output_support : 1; - uint16_t _reserved_for_flags: 3; + uint16_t fast_read_dual_output_support : 1; /* 1-1-2 read */ + uint16_t fast_read_dual_io_support : 1; /* 1-2-2 read */ + uint16_t _reserved_for_flags: 2; /* Block protection. Currently used by Winbond. */ uint16_t protection_granularity_shift : 5; uint16_t bp_bits : 3; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 9fe0492..8f93e3b 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -101,12 +101,14 @@ .id[0] = 0x4014, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, }, { /* W25Q16_V */ .id[0] = 0x4015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -115,6 +117,7 @@ .id[0] = 0x6015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -123,6 +126,7 @@ .id[0] = 0x4016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -131,6 +135,7 @@ .id[0] = 0x6016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -139,6 +144,7 @@ .id[0] = 0x4017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 17, .bp_bits = 3, }, @@ -147,6 +153,7 @@ .id[0] = 0x6017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 17, .bp_bits = 3, }, @@ -155,6 +162,7 @@ .id[0] = 0x8017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 17, .bp_bits = 3, }, @@ -163,6 +171,7 @@ .id[0] = 0x4018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -171,6 +180,7 @@ .id[0] = 0x6018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -179,6 +189,7 @@ .id[0] = 0x7018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -187,6 +198,7 @@ .id[0] = 0x8018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -195,6 +207,7 @@ .id[0] = 0x8020, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 4, }, @@ -203,6 +216,7 @@ .id[0] = 0x4019, .nr_sectors_shift = 13, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 4, }, @@ -211,6 +225,7 @@ .id[0] = 0x7019, .nr_sectors_shift = 13, .fast_read_dual_output_support = 1, + .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 4, }, diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index a7f707e..fe77e3e 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -86,8 +86,9 @@ union { u8 raw; struct { - u8 dual_spi : 1; - u8 _reserved : 7; + u8 dual_output : 1; + u8 dual_io : 1; + u8 _reserved : 6; }; } flags; u16 model; -- To view, visit https://review.coreboot.org/c/coreboot/+/56287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Gerrit-Change-Number: 56287 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: google/trogdor: Enable SPI_FLASH_MACRONIX
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56288 ) Change subject: google/trogdor: Enable SPI_FLASH_MACRONIX ...................................................................... google/trogdor: Enable SPI_FLASH_MACRONIX We may want to use that flash vendor on future variants. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56288 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/trogdor/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 6e6c7d2..e29fd9f 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -30,8 +30,9 @@ select DRIVERS_TI_SN65DSI86BRIDGE select SOC_QUALCOMM_SC7180 select SPI_FLASH - select SPI_FLASH_WINBOND + select SPI_FLASH_MACRONIX select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_BUBS select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_BUBS -- To view, visit https://review.coreboot.org/c/coreboot/+/56288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f Gerrit-Change-Number: 56288 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: google/trogdor: Enable SPI_FLASH_MACRONIX
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Shelley Chen. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56288 ) Change subject: google/trogdor: Enable SPI_FLASH_MACRONIX ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c0fa87fd3f8de8f928e5f41eae2a78204597b5f Gerrit-Change-Number: 56288 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:04:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/gma: Restructure Opregion version info code
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56168 ) Change subject: drivers/intel/gma: Restructure Opregion version info code ...................................................................... drivers/intel/gma: Restructure Opregion version info code Define a structure for opregion version information to align with spec/kernel. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56168 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h 2 files changed, 15 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 799c7fd..1385092 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -255,6 +255,12 @@ return CB_ERR; } +/* Function to get the IGD Opregion version */ +static struct opregion_version opregion_get_version(void) +{ + return (struct opregion_version) { .major = 2, .minor = 0 }; +} + /* * Function to determine if we need to use extended VBT region to pass * VBT pointer. If VBT size > 6 KiB then we need to use extended VBT @@ -333,29 +339,12 @@ rdev_munmap(&rdev, vbt); + /* Get the opregion version information */ + opregion->header.opver = opregion_get_version(); + /* 8kb */ opregion->header.size = sizeof(igd_opregion_t) / 1024; - /* - * Left-shift version field to accommodate Intel Windows driver quirk - * when not using a VBIOS. - * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver. - * - * Tested on: (platform, GPU, windows driver version) - * samsung/stumpy (SNB, GT2, 9.17.10.4459) - * google/link (IVB, GT2, 15.33.4653) - * google/wolf (HSW, GT1, 15.40.36.4703) - * google/panther (HSW, GT2, 15.40.36.4703) - * google/rikku (BDW, GT1, 15.40.36.4703) - * google/lulu (BDW, GT2, 15.40.36.4703) - * google/chell (SKL-Y, GT2, 15.45.21.4821) - * google/sentry (SKL-U, GT1, 15.45.21.4821) - * purism/librem13v2 (SKL-U, GT2, 15.45.21.4821) - * - * No adverse effects when using VBIOS or booting Linux. - */ - opregion->header.version = IGD_OPREGION_VERSION << 24; - // FIXME We just assume we're mobile for now opregion->header.mailboxes = MAILBOXES_MOBILE; diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 879017b..e363921 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -17,7 +17,12 @@ typedef struct { u8 signature[16]; /* Offset 0 OpRegion signature */ u32 size; /* Offset 16 OpRegion size */ - u32 version; /* Offset 20 OpRegion structure version */ + struct opregion_version { + u8 rsvd; + u8 revision; + u8 minor; + u8 major; + } opver; /* Offset 20 OpRegion version structure */ u8 sbios_version[32]; /* Offset 24 System BIOS build version */ u8 vbios_version[16]; /* Offset 56 Video BIOS build version */ u8 driver_version[16]; /* Offset 72 Graphic drvr build version */ @@ -29,7 +34,6 @@ } __packed opregion_header_t; #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" -#define IGD_OPREGION_VERSION 2 #define IGD_MBOX1 (1 << 0) #define IGD_MBOX2 (1 << 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/56168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93a9f2df186002a4e38caa910f867bce0b97ac2b Gerrit-Change-Number: 56168 Gerrit-PatchSet: 13 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDs
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56299 ) Change subject: soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDs ...................................................................... soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDs Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and SOC_INTEL_CRASHLOG is selected by the SoC user. Change-Id: Ibcd0259da86c8d9853e6cc4983675ac97df46c2d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56299 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index dca84cc..15a11cd 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -197,10 +197,8 @@ m_cfg->TmeEnable = CONFIG(INTEL_TME); /* crashLog config */ - if (CONFIG(SOC_INTEL_CRASHLOG)) { - m_cfg->CpuCrashLogDevice = 1; - m_cfg->CpuCrashLogEnable = 1; - } + m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); + m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/56299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcd0259da86c8d9853e6cc4983675ac97df46c2d Gerrit-Change-Number: 56299 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021