coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Angel Pons (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... Patch Set 7: (2 comments) File src/mainboard/asrock/e3c246d4i/gpio.c: https://review.coreboot.org/c/coreboot/+/56339/comment/0256294d_b7a3f5e9 PS4, Line 16: /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ > > Comments should be trimmed […] See purism/librem_cnl File src/mainboard/asrock/e3c246d4i/romstage.c: https://review.coreboot.org/c/coreboot/+/56339/comment/4154f2e9_2a21b4f0 PS4, Line 26: 50 > > Out of curiosity, where does this 50 come from? […] In CB:37441 I used 60 for the X11SCH-F, I'd use the same value here. The oryp5 uses 50 because it only has one DIMM per channel. On Haswell, the RdOdt target defaults to 50, and is increased to 60 when any channel contains 2 DIMMs. -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:44:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram option
by Felix Singer (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Nico Huber. Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56342 to review the following change. Change subject: mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram option ...................................................................... mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram option Change-Id: I8c5d6686bf7c694f9d594e3801c79cfd7fb3da80 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/mainboard/kontron/bsl6/cmos.layout M src/mainboard/siemens/chili/cmos.layout 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/56342/1 diff --git a/src/mainboard/kontron/bsl6/cmos.layout b/src/mainboard/kontron/bsl6/cmos.layout index 2ace8ae..0f79dde 100644 --- a/src/mainboard/kontron/bsl6/cmos.layout +++ b/src/mainboard/kontron/bsl6/cmos.layout @@ -22,6 +22,7 @@ 440 1 e 2 ethernet1 441 1 e 2 ethernet2 442 1 e 2 ethernet3 +443 1 e 1 inhibit_flashlock # payload config options 512 256 s 0 boot_devices diff --git a/src/mainboard/siemens/chili/cmos.layout b/src/mainboard/siemens/chili/cmos.layout index 740fdb8..9f0a426 100644 --- a/src/mainboard/siemens/chili/cmos.layout +++ b/src/mainboard/siemens/chili/cmos.layout @@ -23,6 +23,7 @@ # coreboot config options: mainboard 440 1 e 2 ethernet1 +441 1 e 1 inhibit_flashlock # payload config options 512 256 s 0 boot_devices -- To view, visit https://review.coreboot.org/c/coreboot/+/56342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c5d6686bf7c694f9d594e3801c79cfd7fb3da80 Gerrit-Change-Number: 56342 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: Ampton: Resume from suspend on critical battery
by James Chao (Code Review) 15 Jul '21

15 Jul '21

James Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56341 ) Change subject: Ampton: Resume from suspend on critical battery ...................................................................... Ampton: Resume from suspend on critical battery This patch makes Ampton EC wake up AP from s0ix when the state of charge drops to 2%. Demonstrated as follows: 1. Boot Ampton. 2. Run powerd_dbus_suspend. 3. On EC, run battfake 2. 4. System resumes. BUG=b:189540432 BRANCH=Octopus TEST=Verified on Ampton. Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350 --- M src/mainboard/google/octopus/variants/ampton/include/variant/ec.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/56341/1 diff --git a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h index 056eef8..d75938d 100644 --- a/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h +++ b/src/mainboard/google/octopus/variants/ampton/include/variant/ec.h @@ -8,4 +8,9 @@ /* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ #define EC_ENABLE_SYNC_IRQ +#undef MAINBOARD_EC_S0IX_WAKE_EVENTS +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/56341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98d8e6ea185e8782ad675d4668678b341ca5d350 Gerrit-Change-Number: 56341 Gerrit-PatchSet: 1 Gerrit-Owner: James Chao <james_chao(a)asus.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56339 to look at the new patch set (#8). Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... asrock/e3c246d4i: Add Intel Coffee Lake board This board has upstream OpenBMC support so it's quite nice to develop on (with some extra patches to enable access to the host flash). This board very loosely used the prodrive/hermes and system76/oryp5 as a base and inspiration. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running Option ROMs of the 10G NICs. TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,546 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads: FILO: Hook up autoboot options
by Paul Menzel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Martin Roth, Paul Menzel, Stefan Reinauer. Hello build bot (Jenkins), Nico Huber, Martin Roth, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56213 to look at the new patch set (#4). Change subject: payloads: FILO: Hook up autoboot options ...................................................................... payloads: FILO: Hook up autoboot options FILO allows to configure a line to autoboot. Hook this up into coreboot’s build system. TEST=Configure coreboot for QEMU i440fx with FILO as payload and configure: CONFIG_FILO_MASTER=y CONFIG_FILO_USE_AUTOBOOT=y CONFIG_FILO_AUTOBOOT_FILE="hda1:/vmlinuz root=/dev/sda1 console=tty0 console=ttyS0,115200 initrd=hda1:/initrd.img" CONFIG_FILO_AUTOBOOT_DELAY=5 Boot Debian image with: qemu-system-x86_64 -bios /dev/shm/coreboot/build/coreboot.rom -L /dev/shm -enable-kvm -smp cpus=2 -m 1G -hda /dev/shm/debian-32.img -serial stdio -net nic -net user,hostfwd=tcp::22222-:22 Change-Id: Id167e9a144bf466da87469108002672b299b702a Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/external/FILO/Kconfig M payloads/external/FILO/Makefile M payloads/external/Makefile.inc 3 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56213/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/56213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id167e9a144bf466da87469108002672b299b702a Gerrit-Change-Number: 56213 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Angel Pons (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... Patch Set 7: (1 comment) File src/mainboard/asrock/e3c246d4i/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56339/comment/2c1104b9_03831f64 PS4, Line 107: device pci 1b.0 on # PCI Express Port 17 > > What is this used for? Avoiding coalescing? […] Right, you'd have to tell FSP that a RP is implemented as a slot. -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:33:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: src: Use initial_lapicid() instead of open coding it
by Marshall Dawson (Code Review) 15 Jul '21

15 Jul '21

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55063 ) Change subject: src: Use initial_lapicid() instead of open coding it ...................................................................... Patch Set 6: Code-Review+2 (1 comment) File src/drivers/amd/agesa/eventlog.c: https://review.coreboot.org/c/coreboot/+/55063/comment/5e1134ec_4aba2286 PS1, Line 101: task->apic_id = (u8)initial_lapicid(); > I don't think any of the old parts support x2APIC. Correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/55063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Gerrit-Change-Number: 55063 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:33:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pc80/rtc: Make use of alt-century byte configurable
by Werner Zeh (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Nico Huber. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56214 ) Change subject: drivers/pc80/rtc: Make use of alt-century byte configurable ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: > Werner, I remember that you had some trouble with the RTC piece, so what's your opinion on this? Sorry for being bad responsive here, just to busy right now. Regarding this issue, I have fixed the ugly part of it in the linux kernel and pushed a patch [1]. I guess with this in the background at least the case I was facing should be fixed. Together with CB:54914 the case I had should not happen again, so I am OK with this patch. And in addition CB:56218 does basically what I have started to address in CB:55012 (but sadly haven't had any time to finish it). [1] https://lkml.org/lkml/2021/6/14/816 -- To view, visit https://review.coreboot.org/c/coreboot/+/56214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba3d77120c2474393ac5e64faac1baeeb58c893 Gerrit-Change-Number: 56214 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:29:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr
by Marshall Dawson (Code Review) 15 Jul '21

15 Jul '21

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56246 ) Change subject: include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msr ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: I'm late to the party, but I concur. -- To view, visit https://review.coreboot.org/c/coreboot/+/56246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Gerrit-Change-Number: 56246 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:14:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/brya: Enable south XHCI ports 1 and 2"
by Subrata Banik (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Ronak Kanabar, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56132 ) Change subject: Revert "mb/google/brya: Enable south XHCI ports 1 and 2" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Gerrit-Change-Number: 56132 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:11:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2021