coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/common/block/cpu/mca: commonize mca_check_all_banks
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56313 ) Change subject: soc/amd/common/block/cpu/mca: commonize mca_check_all_banks ...................................................................... soc/amd/common/block/cpu/mca: commonize mca_check_all_banks Since we don't need to skip the MCA check on cold boot on MCAX capable systems, add a mca_skip_check implementation that always returns false. Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/cpu/mca/mca.c M src/soc/amd/common/block/cpu/mca/mca_common.c M src/soc/amd/common/block/cpu/mca/mca_common_defs.h M src/soc/amd/common/block/cpu/mca/mcax.c 4 files changed, 43 insertions(+), 55 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/mca/mca.c b/src/soc/amd/common/block/cpu/mca/mca.c index 1c3a30c..48c0286 100644 --- a/src/soc/amd/common/block/cpu/mca/mca.c +++ b/src/soc/amd/common/block/cpu/mca/mca.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/mca.h> #include <amdblocks/reset.h> #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> @@ -9,12 +8,12 @@ #include <types.h> #include "mca_common_defs.h" -static bool mca_skip_check(void) +bool mca_skip_check(void) { return !is_warm_reset(); } -static void mca_print_error(unsigned int bank) +void mca_print_error(unsigned int bank) { msr_t msr; @@ -32,29 +31,3 @@ msr = rdmsr(MC_CTL_MASK(bank)); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } - -void mca_check_all_banks(void) -{ - struct mca_bank_status mci; - const unsigned int num_banks = mca_get_bank_count(); - - if (!mca_has_expected_bank_count()) - printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); - - if (mca_skip_check()) - return; - - for (unsigned int i = 0 ; i < num_banks ; i++) { - if (!mca_is_valid_bank(i)) - continue; - - mci.bank = i; - mci.sts = rdmsr(IA32_MC_STATUS(i)); - if (mci.sts.hi || mci.sts.lo) { - mca_print_error(i); - - if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } - } -} diff --git a/src/soc/amd/common/block/cpu/mca/mca_common.c b/src/soc/amd/common/block/cpu/mca/mca_common.c index f029966..b357691 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_common.c +++ b/src/soc/amd/common/block/cpu/mca/mca_common.c @@ -2,8 +2,38 @@ #include <amdblocks/mca.h> #include <cpu/x86/msr.h> +#include <console/console.h> +#include <types.h> #include "mca_common_defs.h" +static void mca_check_all_banks(void) +{ + struct mca_bank_status mci; + const unsigned int num_banks = mca_get_bank_count(); + + if (!mca_has_expected_bank_count()) + printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); + + if (mca_skip_check()) + return; + + for (unsigned int i = 0 ; i < num_banks ; i++) { + if (!mca_is_valid_bank(i)) + continue; + + mci.bank = i; + /* The MCA status register can be used in both the MCA and MCAX case */ + mci.sts = rdmsr(IA32_MC_STATUS(i)); + if (mci.sts.hi || mci.sts.lo) { + mca_print_error(i); + + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) + build_bert_mca_error(&mci); + } + } +} + + void check_mca(void) { mca_check_all_banks(); diff --git a/src/soc/amd/common/block/cpu/mca/mca_common_defs.h b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h index 8142371..910965a 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_common_defs.h +++ b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h @@ -5,8 +5,10 @@ #include <amdblocks/mca.h> #include <cper.h> +#include <types.h> -void mca_check_all_banks(void); +bool mca_skip_check(void); +void mca_print_error(unsigned int bank); void build_bert_mca_error(struct mca_bank_status *mci); enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci); void fill_generic_section(cper_proc_generic_error_section_t *sec, struct mca_bank_status *mci); diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c index fecac0a..b8fa0c0 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax.c +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/mca.h> #include <amdblocks/msr_zen.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> @@ -8,7 +7,14 @@ #include <types.h> #include "mca_common_defs.h" -static void mca_print_error(unsigned int bank) +bool mca_skip_check(void) +{ + /* On Zen-based CPUs/APUs the MCA(X) status register have a defined state even in the + cold boot path, so no need to skip the check */ + return false; +} + +void mca_print_error(unsigned int bank) { msr_t msr; @@ -26,26 +32,3 @@ msr = rdmsr(MCA_CTL_MASK_MSR(bank)); printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); } - -void mca_check_all_banks(void) -{ - struct mca_bank_status mci; - const unsigned int num_banks = mca_get_bank_count(); - - if (!mca_has_expected_bank_count()) - printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); - - for (unsigned int i = 0 ; i < num_banks ; i++) { - if (!mca_is_valid_bank(i)) - continue; - - mci.bank = i; - mci.sts = rdmsr(MCAX_STATUS_MSR(i)); - if (mci.sts.hi || mci.sts.lo) { - mca_print_error(i); - - if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/56313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d Gerrit-Change-Number: 56313 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: lib/thread: Verify threads are initialized before yielding
by Krystian Hebel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Raul Rangel. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56318 ) Change subject: lib/thread: Verify threads are initialized before yielding ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56318/comment/215fe4ea_d6af6a75 PS1, Line 11: setup > set up Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43 Gerrit-Change-Number: 56318 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 17:18:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/thread: Verify threads are initialized before yielding
by Raul Rangel (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Raul Rangel. Hello build bot (Jenkins), Furquan Shaikh, Julius Werner, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56318 to look at the new patch set (#2). Change subject: lib/thread: Verify threads are initialized before yielding ...................................................................... lib/thread: Verify threads are initialized before yielding In hardwaremain.c we call console_init before threads_initialize. Part of setting up the uart requires calling udelay which then calls thread_yield_microseconds. Since threads have not been set up, trying to yield will result in bad things happening. This change guards the thread methods by making current_thread return NULL if the structures have not been initialized. BUG=b:179699789 TEST=Ramstage no longer hangs with serial enabled Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43 --- M src/lib/thread.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/56318/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9e1eedfaebe584901d2937c8aa24e158706fa43 Gerrit-Change-Number: 56318 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/cpu/mca/mca: factor out mca_skip_check
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56312 ) Change subject: soc/amd/common/block/cpu/mca/mca: factor out mca_skip_check ...................................................................... soc/amd/common/block/cpu/mca/mca: factor out mca_skip_check This will allow moving mca_check_all_banks to mca_common.c. Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/cpu/mca/mca.c 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/mca/mca.c b/src/soc/amd/common/block/cpu/mca/mca.c index b5fd6a2..1c3a30c 100644 --- a/src/soc/amd/common/block/cpu/mca/mca.c +++ b/src/soc/amd/common/block/cpu/mca/mca.c @@ -9,6 +9,11 @@ #include <types.h> #include "mca_common_defs.h" +static bool mca_skip_check(void) +{ + return !is_warm_reset(); +} + static void mca_print_error(unsigned int bank) { msr_t msr; @@ -36,7 +41,7 @@ if (!mca_has_expected_bank_count()) printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); - if (!is_warm_reset()) + if (mca_skip_check()) return; for (unsigned int i = 0 ; i < num_banks ; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23 Gerrit-Change-Number: 56312 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG
by Karthik Ramasubramanian (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Ian Feng, Dtrain Hsu, Henry Sun, Paul Menzel, Shou-Chieh Hsu. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56248 ) Change subject: mb/google/dedede/var/cret: Enable/disable Touchscreen based on FW_CONFIG ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/dedede/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56248/comment/67b4a120_8723f087 PS4, Line 13: field TOUCHSCREEN 5 : option TOUCHSCREEN_ABSENT 0 : option TOUCHSCREEN_PRESENT 1 : end Does this FW config field apply to the entire Dedede design or does it apply only to Cret? -- To view, visit https://review.coreboot.org/c/coreboot/+/56248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice517c034e2dab93bb27e75dccf06d9a0936526b Gerrit-Change-Number: 56248 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 17:04:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56311 ) Change subject: soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count ...................................................................... soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_count This aligns the mca_check_all_banks implementation in the common mca.c with the one in the common mcax.c file. Do the MCA bank count check before the !is_warm_reset() check, so that a mismatch also gets printed on the cold boot path. Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/cpu/mca/mca.c M src/soc/amd/stoneyridge/mca.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/mca/mca.c b/src/soc/amd/common/block/cpu/mca/mca.c index 2d91894..b5fd6a2 100644 --- a/src/soc/amd/common/block/cpu/mca/mca.c +++ b/src/soc/amd/common/block/cpu/mca/mca.c @@ -33,6 +33,9 @@ struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); + if (!mca_has_expected_bank_count()) + printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); + if (!is_warm_reset()) return; diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 240e75d..7ca16a8 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> +#include <cpu/x86/msr.h> #include <types.h> static const char *const mca_bank_name[] = { @@ -15,6 +16,11 @@ [6] = "Floating point unit" }; +bool mca_has_expected_bank_count(void) +{ + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); +} + bool mca_is_valid_bank(unsigned int bank) { return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/56311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa Gerrit-Change-Number: 56311 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/cpu/mca: move function prototypes to local header
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56309 ) Change subject: soc/amd/common/block/cpu/mca: move function prototypes to local header ...................................................................... soc/amd/common/block/cpu/mca: move function prototypes to local header Since those functions are implemented and used only inside the common MCA(X) code, there's no need to have them in the header file that gets included in the SoC-specific code. Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/cpu/mca/mca.c M src/soc/amd/common/block/cpu/mca/mca_common.c M src/soc/amd/common/block/cpu/mca/mca_common_defs.h M src/soc/amd/common/block/cpu/mca/mcax.c M src/soc/amd/common/block/include/amdblocks/mca.h 5 files changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/mca/mca.c b/src/soc/amd/common/block/cpu/mca/mca.c index c7d3e6f..2d91894 100644 --- a/src/soc/amd/common/block/cpu/mca/mca.c +++ b/src/soc/amd/common/block/cpu/mca/mca.c @@ -7,6 +7,7 @@ #include <cpu/x86/msr.h> #include <console/console.h> #include <types.h> +#include "mca_common_defs.h" static void mca_print_error(unsigned int bank) { diff --git a/src/soc/amd/common/block/cpu/mca/mca_common.c b/src/soc/amd/common/block/cpu/mca/mca_common.c index 0a37508..f029966 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_common.c +++ b/src/soc/amd/common/block/cpu/mca/mca_common.c @@ -2,6 +2,7 @@ #include <amdblocks/mca.h> #include <cpu/x86/msr.h> +#include "mca_common_defs.h" void check_mca(void) { diff --git a/src/soc/amd/common/block/cpu/mca/mca_common_defs.h b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h index 41d73d8..8142371 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_common_defs.h +++ b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h @@ -6,6 +6,8 @@ #include <amdblocks/mca.h> #include <cper.h> +void mca_check_all_banks(void); +void build_bert_mca_error(struct mca_bank_status *mci); enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci); void fill_generic_section(cper_proc_generic_error_section_t *sec, struct mca_bank_status *mci); diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c index cb01e1d..fecac0a 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax.c +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -6,6 +6,7 @@ #include <cpu/x86/msr.h> #include <console/console.h> #include <types.h> +#include "mca_common_defs.h" static void mca_print_error(unsigned int bank) { diff --git a/src/soc/amd/common/block/include/amdblocks/mca.h b/src/soc/amd/common/block/include/amdblocks/mca.h index 70a83ab..c84f232 100644 --- a/src/soc/amd/common/block/include/amdblocks/mca.h +++ b/src/soc/amd/common/block/include/amdblocks/mca.h @@ -12,8 +12,6 @@ }; void check_mca(void); -void mca_check_all_banks(void); -void build_bert_mca_error(struct mca_bank_status *mci); bool mca_has_expected_bank_count(void); bool mca_is_valid_bank(unsigned int bank); const char *mca_get_bank_name(unsigned int bank); -- To view, visit https://review.coreboot.org/c/coreboot/+/56309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d Gerrit-Change-Number: 56309 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/mca: factor out common MCA/MCAX check & print functionality
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56290 ) Change subject: soc/amd/*/mca: factor out common MCA/MCAX check & print functionality ...................................................................... soc/amd/*/mca: factor out common MCA/MCAX check & print functionality For Cezanne stubs are added for the functions that the SoC-specific code needs to provide. Since the mca_is_valid_bank stub on Cezanne always returns false, the checks get skipped for it at the moment. The actual functionality will be added in a later patch. Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/cezanne/mca.c M src/soc/amd/common/block/cpu/mca/Makefile.inc A src/soc/amd/common/block/cpu/mca/mca.c A src/soc/amd/common/block/cpu/mca/mcax.c M src/soc/amd/common/block/include/amdblocks/mca.h M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 7 files changed, 132 insertions(+), 101 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/mca.c b/src/soc/amd/cezanne/mca.c index 68fae29..77006a7 100644 --- a/src/soc/amd/cezanne/mca.c +++ b/src/soc/amd/cezanne/mca.c @@ -1,8 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> +#include <types.h> -void mca_check_all_banks(void) +bool mca_has_expected_bank_count(void) { - /* TODO: Implement MCAX register checking and BERT table generation. */ + return true; +} + +bool mca_is_valid_bank(unsigned int bank) +{ + return false; +} + +const char *mca_get_bank_name(unsigned int bank) +{ + return ""; } diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.inc b/src/soc/amd/common/block/cpu/mca/Makefile.inc index 61d6974..0232805 100644 --- a/src/soc/amd/common/block/cpu/mca/Makefile.inc +++ b/src/soc/amd/common/block/cpu/mca/Makefile.inc @@ -3,5 +3,12 @@ ramstage-y += mca_common_bert.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA) += mca_bert.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCAX) += mcax_bert.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCA),y) +ramstage-y += mca_bert.c +ramstage-y += mca.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCA + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCAX),y) +ramstage-y += mcax_bert.c +ramstage-y += mcax.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/common/block/cpu/mca/mca.c b/src/soc/amd/common/block/cpu/mca/mca.c new file mode 100644 index 0000000..c7d3e6f --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mca.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <amdblocks/reset.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <types.h> + +static void mca_print_error(unsigned int bank) +{ + msr_t msr; + + printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, + mca_get_bank_name(bank)); + + msr = rdmsr(IA32_MC_STATUS(bank)); + printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC_ADDR(bank)); + printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC_MISC(bank)); + printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(IA32_MC_CTL(bank)); + printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MC_CTL_MASK(bank)); + printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); +} + +void mca_check_all_banks(void) +{ + struct mca_bank_status mci; + const unsigned int num_banks = mca_get_bank_count(); + + if (!is_warm_reset()) + return; + + for (unsigned int i = 0 ; i < num_banks ; i++) { + if (!mca_is_valid_bank(i)) + continue; + + mci.bank = i; + mci.sts = rdmsr(IA32_MC_STATUS(i)); + if (mci.sts.hi || mci.sts.lo) { + mca_print_error(i); + + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) + build_bert_mca_error(&mci); + } + } +} diff --git a/src/soc/amd/common/block/cpu/mca/mcax.c b/src/soc/amd/common/block/cpu/mca/mcax.c new file mode 100644 index 0000000..cb01e1d --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mcax.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <amdblocks/msr_zen.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <types.h> + +static void mca_print_error(unsigned int bank) +{ + msr_t msr; + + printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, + mca_get_bank_name(bank)); + + msr = rdmsr(MCAX_STATUS_MSR(bank)); + printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCAX_ADDR_MSR(bank)); + printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCAX_MISC0_MSR(bank)); + printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCAX_CTL_MSR(bank)); + printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); + msr = rdmsr(MCA_CTL_MASK_MSR(bank)); + printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); +} + +void mca_check_all_banks(void) +{ + struct mca_bank_status mci; + const unsigned int num_banks = mca_get_bank_count(); + + if (!mca_has_expected_bank_count()) + printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); + + for (unsigned int i = 0 ; i < num_banks ; i++) { + if (!mca_is_valid_bank(i)) + continue; + + mci.bank = i; + mci.sts = rdmsr(MCAX_STATUS_MSR(i)); + if (mci.sts.hi || mci.sts.lo) { + mca_print_error(i); + + if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) + build_bert_mca_error(&mci); + } + } +} diff --git a/src/soc/amd/common/block/include/amdblocks/mca.h b/src/soc/amd/common/block/include/amdblocks/mca.h index 7cead26..70a83ab 100644 --- a/src/soc/amd/common/block/include/amdblocks/mca.h +++ b/src/soc/amd/common/block/include/amdblocks/mca.h @@ -4,6 +4,7 @@ #define AMD_BLOCK_MCA_H #include <cpu/x86/msr.h> +#include <types.h> struct mca_bank_status { unsigned int bank; @@ -13,5 +14,8 @@ void check_mca(void); void mca_check_all_banks(void); void build_bert_mca_error(struct mca_bank_status *mci); +bool mca_has_expected_bank_count(void); +bool mca_is_valid_bank(unsigned int bank); +const char *mca_get_bank_name(unsigned int bank); #endif /* AMD_BLOCK_MCA_H */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index c41708c..91b58ac 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -1,10 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> -#include <amdblocks/msr_zen.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> -#include <console/console.h> #include <types.h> static const char *const mca_bank_name[] = { @@ -33,62 +30,20 @@ [22] = "PIE", }; -static bool mca_has_expected_bank_count(void) +bool mca_has_expected_bank_count(void) { return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); } -static bool mca_is_valid_bank(unsigned int bank) +bool mca_is_valid_bank(unsigned int bank) { return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); } -static const char *mca_get_bank_name(unsigned int bank) +const char *mca_get_bank_name(unsigned int bank) { if (mca_is_valid_bank(bank)) return mca_bank_name[bank]; else return ""; } - -static void mca_print_error(unsigned int bank) -{ - msr_t msr; - - printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, - mca_get_bank_name(bank)); - - msr = rdmsr(MCAX_STATUS_MSR(bank)); - printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MCAX_ADDR_MSR(bank)); - printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MCAX_MISC0_MSR(bank)); - printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MCAX_CTL_MSR(bank)); - printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MCA_CTL_MASK_MSR(bank)); - printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); -} - -void mca_check_all_banks(void) -{ - struct mca_bank_status mci; - const unsigned int num_banks = mca_get_bank_count(); - - if (!mca_has_expected_bank_count()) - printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); - - for (unsigned int i = 0 ; i < num_banks ; i++) { - if (!mca_is_valid_bank(i)) - continue; - - mci.bank = i; - mci.sts = rdmsr(MCAX_STATUS_MSR(i)); - if (mci.sts.hi || mci.sts.lo) { - mca_print_error(i); - - if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } - } -} diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 566f54c..240e75d 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,11 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/mca.h> -#include <amdblocks/reset.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/msr.h> -#include <console/console.h> #include <types.h> static const char *const mca_bank_name[] = { @@ -20,57 +15,15 @@ [6] = "Floating point unit" }; -static bool mca_is_valid_bank(unsigned int bank) +bool mca_is_valid_bank(unsigned int bank) { return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); } -static const char *mca_get_bank_name(unsigned int bank) +const char *mca_get_bank_name(unsigned int bank) { if (mca_is_valid_bank(bank)) return mca_bank_name[bank]; else return ""; } - -static void mca_print_error(unsigned int bank) -{ - msr_t msr; - - printk(BIOS_WARNING, "#MC Error: core %u, bank %u %s\n", initial_lapicid(), bank, - mca_get_bank_name(bank)); - - msr = rdmsr(IA32_MC_STATUS(bank)); - printk(BIOS_WARNING, " MC%u_STATUS = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC_ADDR(bank)); - printk(BIOS_WARNING, " MC%u_ADDR = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC_MISC(bank)); - printk(BIOS_WARNING, " MC%u_MISC = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(IA32_MC_CTL(bank)); - printk(BIOS_WARNING, " MC%u_CTL = %08x_%08x\n", bank, msr.hi, msr.lo); - msr = rdmsr(MC_CTL_MASK(bank)); - printk(BIOS_WARNING, " MC%u_CTL_MASK = %08x_%08x\n", bank, msr.hi, msr.lo); -} - -void mca_check_all_banks(void) -{ - struct mca_bank_status mci; - const unsigned int num_banks = mca_get_bank_count(); - - if (!is_warm_reset()) - return; - - for (unsigned int i = 0 ; i < num_banks ; i++) { - if (!mca_is_valid_bank(i)) - continue; - - mci.bank = i; - mci.sts = rdmsr(IA32_MC_STATUS(i)); - if (mci.sts.hi || mci.sts.lo) { - mca_print_error(i); - - if (CONFIG(ACPI_BERT) && mca_valid(mci.sts)) - build_bert_mca_error(&mci); - } - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/56290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Gerrit-Change-Number: 56290 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/mca: factor out mca_has_expected_bank_count
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56294 ) Change subject: soc/amd/picasso/mca: factor out mca_has_expected_bank_count ...................................................................... soc/amd/picasso/mca: factor out mca_has_expected_bank_count To factor out the rest of the common MCAX code, mca_bank_name[] may only be accessed by accessor functions, so implement this for the last place that still accessed mca_bank_name[] directly. Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/mca.c 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 3c5b63f..c41708c 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -33,6 +33,11 @@ [22] = "PIE", }; +static bool mca_has_expected_bank_count(void) +{ + return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count(); +} + static bool mca_is_valid_bank(unsigned int bank) { return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL); @@ -70,7 +75,7 @@ struct mca_bank_status mci; const unsigned int num_banks = mca_get_bank_count(); - if (ARRAY_SIZE(mca_bank_name) != num_banks) + if (!mca_has_expected_bank_count()) printk(BIOS_WARNING, "CPU has an unexpected number of MCA banks!\n"); for (unsigned int i = 0 ; i < num_banks ; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9 Gerrit-Change-Number: 56294 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/blocks/cpu/mca: factor out common BERT helper functions
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56284 ) Change subject: soc/amd/common/blocks/cpu/mca: factor out common BERT helper functions ...................................................................... soc/amd/common/blocks/cpu/mca: factor out common BERT helper functions Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56284 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/cpu/mca/Makefile.inc M src/soc/amd/common/block/cpu/mca/mca_bert.c A src/soc/amd/common/block/cpu/mca/mca_common_bert.c A src/soc/amd/common/block/cpu/mca/mca_common_defs.h M src/soc/amd/common/block/cpu/mca/mcax_bert.c 5 files changed, 60 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.inc b/src/soc/amd/common/block/cpu/mca/Makefile.inc index 5c1d2c5..61d6974 100644 --- a/src/soc/amd/common/block/cpu/mca/Makefile.inc +++ b/src/soc/amd/common/block/cpu/mca/Makefile.inc @@ -1,3 +1,7 @@ -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON) += mca_common.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON),y) +ramstage-y += mca_common.c +ramstage-y += mca_common_bert.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON + ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA) += mca_bert.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCAX) += mcax_bert.c diff --git a/src/soc/amd/common/block/cpu/mca/mca_bert.c b/src/soc/amd/common/block/cpu/mca/mca_bert.c index ffd8973..93d5749 100644 --- a/src/soc/amd/common/block/cpu/mca/mca_bert.c +++ b/src/soc/amd/common/block/cpu/mca/mca_bert.c @@ -8,6 +8,7 @@ #include <arch/bert_storage.h> #include <cper.h> #include <types.h> +#include "mca_common_defs.h" static inline size_t mca_report_size_reqd(void) { @@ -36,41 +37,6 @@ return size; } -static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) -{ - int error = mca_err_type(mci->sts); - - if (error == MCA_ERRTYPE_BUS) - return X86_PROCESSOR_BUS_CHK; - if (error == MCA_ERRTYPE_INT) - return X86_PROCESSOR_MS_CHK; - if (error == MCA_ERRTYPE_MEM) - return X86_PROCESSOR_CACHE_CHK; - if (error == MCA_ERRTYPE_TLB) - return X86_PROCESSOR_TLB_CHK; - - return X86_PROCESSOR_MS_CHK; /* unrecognized */ -} - -/* Fill additional information in the Generic Processor Error Section. */ -static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank_status *mci) -{ - int type = mca_err_type(mci->sts); - - if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ - sec->error_type = GENPROC_ERRTYPE_BUS; - else if (type == MCA_ERRTYPE_INT) - sec->error_type = GENPROC_ERRTYPE_UARCH; - else if (type == MCA_ERRTYPE_MEM) - sec->error_type = GENPROC_ERRTYPE_CACHE; - else if (type == MCA_ERRTYPE_TLB) - sec->error_type = GENPROC_ERRTYPE_TLB; - else - sec->error_type = GENPROC_ERRTYPE_UNKNOWN; - sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; -} - /* Convert an error reported by an MCA bank into BERT information to be reported * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, * which is the best method to report MSR context. As a result, add two diff --git a/src/soc/amd/common/block/cpu/mca/mca_common_bert.c b/src/soc/amd/common/block/cpu/mca/mca_common_bert.c new file mode 100644 index 0000000..53a73d6 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mca_common_bert.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <cper.h> +#include <types.h> +#include "mca_common_defs.h" + +enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) +{ + int error = mca_err_type(mci->sts); + + if (error == MCA_ERRTYPE_BUS) + return X86_PROCESSOR_BUS_CHK; + if (error == MCA_ERRTYPE_INT) + return X86_PROCESSOR_MS_CHK; + if (error == MCA_ERRTYPE_MEM) + return X86_PROCESSOR_CACHE_CHK; + if (error == MCA_ERRTYPE_TLB) + return X86_PROCESSOR_TLB_CHK; + + return X86_PROCESSOR_MS_CHK; /* unrecognized */ +} + +/* Fill additional information in the Generic Processor Error Section. */ +void fill_generic_section(cper_proc_generic_error_section_t *sec, + struct mca_bank_status *mci) +{ + int type = mca_err_type(mci->sts); + + if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ + sec->error_type = GENPROC_ERRTYPE_BUS; + else if (type == MCA_ERRTYPE_INT) + sec->error_type = GENPROC_ERRTYPE_UARCH; + else if (type == MCA_ERRTYPE_MEM) + sec->error_type = GENPROC_ERRTYPE_CACHE; + else if (type == MCA_ERRTYPE_TLB) + sec->error_type = GENPROC_ERRTYPE_TLB; + else + sec->error_type = GENPROC_ERRTYPE_UNKNOWN; + sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; +} diff --git a/src/soc/amd/common/block/cpu/mca/mca_common_defs.h b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h new file mode 100644 index 0000000..41d73d8 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mca_common_defs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_MCA_COMMON_DEF_H +#define AMD_BLOCK_MCA_COMMON_DEF_H + +#include <amdblocks/mca.h> +#include <cper.h> + +enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci); +void fill_generic_section(cper_proc_generic_error_section_t *sec, struct mca_bank_status *mci); + +#endif /* AMD_BLOCK_MCA_COMMON_DEF_H */ diff --git a/src/soc/amd/common/block/cpu/mca/mcax_bert.c b/src/soc/amd/common/block/cpu/mca/mcax_bert.c index f976158..8d864e8 100644 --- a/src/soc/amd/common/block/cpu/mca/mcax_bert.c +++ b/src/soc/amd/common/block/cpu/mca/mcax_bert.c @@ -8,6 +8,7 @@ #include <arch/bert_storage.h> #include <cper.h> #include <types.h> +#include "mca_common_defs.h" /* MISC4 is the last used register in the MCAX banks of Picasso */ #define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) @@ -40,41 +41,6 @@ return size; } -static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) -{ - int error = mca_err_type(mci->sts); - - if (error == MCA_ERRTYPE_BUS) - return X86_PROCESSOR_BUS_CHK; - if (error == MCA_ERRTYPE_INT) - return X86_PROCESSOR_MS_CHK; - if (error == MCA_ERRTYPE_MEM) - return X86_PROCESSOR_CACHE_CHK; - if (error == MCA_ERRTYPE_TLB) - return X86_PROCESSOR_TLB_CHK; - - return X86_PROCESSOR_MS_CHK; /* unrecognized */ -} - -/* Fill additional information in the Generic Processor Error Section. */ -static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank_status *mci) -{ - int type = mca_err_type(mci->sts); - - if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ - sec->error_type = GENPROC_ERRTYPE_BUS; - else if (type == MCA_ERRTYPE_INT) - sec->error_type = GENPROC_ERRTYPE_UARCH; - else if (type == MCA_ERRTYPE_MEM) - sec->error_type = GENPROC_ERRTYPE_CACHE; - else if (type == MCA_ERRTYPE_TLB) - sec->error_type = GENPROC_ERRTYPE_TLB; - else - sec->error_type = GENPROC_ERRTYPE_UNKNOWN; - sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; -} - /* Convert an error reported by an MCA bank into BERT information to be reported * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, * which is the best method to report MSR context. As a result, add two -- To view, visit https://review.coreboot.org/c/coreboot/+/56284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5 Gerrit-Change-Number: 56284 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021