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Change in coreboot[master]: soc/amd/*/mca: factor out BERT entry generation to soc/amd/common
by Felix Held (Code Review) 15 Jul '21

15 Jul '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56283 ) Change subject: soc/amd/*/mca: factor out BERT entry generation to soc/amd/common ...................................................................... soc/amd/*/mca: factor out BERT entry generation to soc/amd/common Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/cpu/mca/Makefile.inc A src/soc/amd/common/block/cpu/mca/mca_bert.c A src/soc/amd/common/block/cpu/mca/mcax_bert.c M src/soc/amd/common/block/include/amdblocks/mca.h M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c 6 files changed, 268 insertions(+), 255 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/mca/Makefile.inc b/src/soc/amd/common/block/cpu/mca/Makefile.inc index 0aa47e1..5c1d2c5 100644 --- a/src/soc/amd/common/block/cpu/mca/Makefile.inc +++ b/src/soc/amd/common/block/cpu/mca/Makefile.inc @@ -1 +1,3 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON) += mca_common.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCA) += mca_bert.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_MCAX) += mcax_bert.c diff --git a/src/soc/amd/common/block/cpu/mca/mca_bert.c b/src/soc/amd/common/block/cpu/mca/mca_bert.c new file mode 100644 index 0000000..ffd8973 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mca_bert.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> +#include <acpi/acpi.h> +#include <console/console.h> +#include <arch/bert_storage.h> +#include <cper.h> +#include <types.h> + +static inline size_t mca_report_size_reqd(void) +{ + size_t size; + + size = sizeof(acpi_generic_error_status_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_proc_generic_error_section_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_ia32x64_proc_error_section_t); + + /* Check Error */ + size += cper_ia32x64_check_sz(); + + /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); + + /* Context of MCi_CTL, MCi_STATUS, MCi_ADDR, MCi_MISC */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 4); + + /* Context of CTL_MASK */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); + + return size; +} + +static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) +{ + int error = mca_err_type(mci->sts); + + if (error == MCA_ERRTYPE_BUS) + return X86_PROCESSOR_BUS_CHK; + if (error == MCA_ERRTYPE_INT) + return X86_PROCESSOR_MS_CHK; + if (error == MCA_ERRTYPE_MEM) + return X86_PROCESSOR_CACHE_CHK; + if (error == MCA_ERRTYPE_TLB) + return X86_PROCESSOR_TLB_CHK; + + return X86_PROCESSOR_MS_CHK; /* unrecognized */ +} + +/* Fill additional information in the Generic Processor Error Section. */ +static void fill_generic_section(cper_proc_generic_error_section_t *sec, + struct mca_bank_status *mci) +{ + int type = mca_err_type(mci->sts); + + if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ + sec->error_type = GENPROC_ERRTYPE_BUS; + else if (type == MCA_ERRTYPE_INT) + sec->error_type = GENPROC_ERRTYPE_UARCH; + else if (type == MCA_ERRTYPE_MEM) + sec->error_type = GENPROC_ERRTYPE_CACHE; + else if (type == MCA_ERRTYPE_TLB) + sec->error_type = GENPROC_ERRTYPE_TLB; + else + sec->error_type = GENPROC_ERRTYPE_UNKNOWN; + sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; +} + +/* Convert an error reported by an MCA bank into BERT information to be reported + * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, + * which is the best method to report MSR context. As a result, add two + * structures: A "processor generic error" that is parsed, and an IA32/X64 one + * to capture complete information. + * + * Future work may attempt to interpret the specific Family 15h error symptoms + * found in the MCA registers. This data could enhance the reporting of the + * Processor Generic section and the failing error/check added to the + * IA32/X64 section. + */ +void build_bert_mca_error(struct mca_bank_status *mci) +{ + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *gen_entry; + acpi_hest_generic_data_v300_t *x86_entry; + cper_proc_generic_error_section_t *gen_sec; + cper_ia32x64_proc_error_section_t *x86_sec; + cper_ia32x64_proc_error_info_t *chk; + cper_ia32x64_context_t *ctx; + + if (mca_report_size_reqd() > bert_storage_remaining()) + goto failed; + + status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); + if (!status) + goto failed; + + gen_entry = acpi_hest_generic_data3(status); + gen_sec = section_of_acpientry(gen_sec, gen_entry); + + fill_generic_section(gen_sec, mci); + + x86_entry = bert_append_ia32x64(status); + x86_sec = section_of_acpientry(x86_sec, x86_entry); + + chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); + if (!chk) + goto failed; + + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MC_CTL_MASK(mci->bank), 1); + if (!ctx) + goto failed; + + return; + +failed: + /* We're here because of a hardware error, don't break something else */ + printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); +} diff --git a/src/soc/amd/common/block/cpu/mca/mcax_bert.c b/src/soc/amd/common/block/cpu/mca/mcax_bert.c new file mode 100644 index 0000000..f976158 --- /dev/null +++ b/src/soc/amd/common/block/cpu/mca/mcax_bert.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/mca.h> +#include <amdblocks/msr_zen.h> +#include <cpu/x86/msr.h> +#include <acpi/acpi.h> +#include <console/console.h> +#include <arch/bert_storage.h> +#include <cper.h> +#include <types.h> + +/* MISC4 is the last used register in the MCAX banks of Picasso */ +#define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) + +static inline size_t mca_report_size_reqd(void) +{ + size_t size; + + size = sizeof(acpi_generic_error_status_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_proc_generic_error_section_t); + + size += sizeof(acpi_hest_generic_data_v300_t); + size += sizeof(cper_ia32x64_proc_error_section_t); + + /* Check Error */ + size += cper_ia32x64_check_sz(); + + /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); + + /* Context of CTL, STATUS, ADDR, MISC0, CONFIG, IPID, SYND, RESERVED, DESTAT, DEADDR, + MISC1, MISC2, MISC3, MISC4 */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, MCAX_USED_REGISTERS_PER_BANK); + + /* Context of CTL_MASK */ + size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); + + return size; +} + +static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) +{ + int error = mca_err_type(mci->sts); + + if (error == MCA_ERRTYPE_BUS) + return X86_PROCESSOR_BUS_CHK; + if (error == MCA_ERRTYPE_INT) + return X86_PROCESSOR_MS_CHK; + if (error == MCA_ERRTYPE_MEM) + return X86_PROCESSOR_CACHE_CHK; + if (error == MCA_ERRTYPE_TLB) + return X86_PROCESSOR_TLB_CHK; + + return X86_PROCESSOR_MS_CHK; /* unrecognized */ +} + +/* Fill additional information in the Generic Processor Error Section. */ +static void fill_generic_section(cper_proc_generic_error_section_t *sec, + struct mca_bank_status *mci) +{ + int type = mca_err_type(mci->sts); + + if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ + sec->error_type = GENPROC_ERRTYPE_BUS; + else if (type == MCA_ERRTYPE_INT) + sec->error_type = GENPROC_ERRTYPE_UARCH; + else if (type == MCA_ERRTYPE_MEM) + sec->error_type = GENPROC_ERRTYPE_CACHE; + else if (type == MCA_ERRTYPE_TLB) + sec->error_type = GENPROC_ERRTYPE_TLB; + else + sec->error_type = GENPROC_ERRTYPE_UNKNOWN; + sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; +} + +/* Convert an error reported by an MCA bank into BERT information to be reported + * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, + * which is the best method to report MSR context. As a result, add two + * structures: A "processor generic error" that is parsed, and an IA32/X64 one + * to capture complete information. + */ +void build_bert_mca_error(struct mca_bank_status *mci) +{ + acpi_generic_error_status_t *status; + acpi_hest_generic_data_v300_t *gen_entry; + acpi_hest_generic_data_v300_t *x86_entry; + cper_proc_generic_error_section_t *gen_sec; + cper_ia32x64_proc_error_section_t *x86_sec; + cper_ia32x64_proc_error_info_t *chk; + cper_ia32x64_context_t *ctx; + + if (mca_report_size_reqd() > bert_storage_remaining()) + goto failed; + + status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); + if (!status) + goto failed; + + gen_entry = acpi_hest_generic_data3(status); + gen_sec = section_of_acpientry(gen_sec, gen_entry); + + fill_generic_section(gen_sec, mci); + + x86_entry = bert_append_ia32x64(status); + x86_sec = section_of_acpientry(x86_sec, x86_entry); + + chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); + if (!chk) + goto failed; + + ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCAX_CTL_MSR(mci->bank), + MCAX_USED_REGISTERS_PER_BANK); + if (!ctx) + goto failed; + ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCA_CTL_MASK_MSR(mci->bank), 1); + if (!ctx) + goto failed; + + return; + +failed: + /* We're here because of a hardware error, don't break something else */ + printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); +} diff --git a/src/soc/amd/common/block/include/amdblocks/mca.h b/src/soc/amd/common/block/include/amdblocks/mca.h index 16b016b..7cead26 100644 --- a/src/soc/amd/common/block/include/amdblocks/mca.h +++ b/src/soc/amd/common/block/include/amdblocks/mca.h @@ -3,7 +3,15 @@ #ifndef AMD_BLOCK_MCA_H #define AMD_BLOCK_MCA_H +#include <cpu/x86/msr.h> + +struct mca_bank_status { + unsigned int bank; + msr_t sts; +}; + void check_mca(void); void mca_check_all_banks(void); +void build_bert_mca_error(struct mca_bank_status *mci); #endif /* AMD_BLOCK_MCA_H */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 074f313..3c5b63f 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -2,139 +2,11 @@ #include <amdblocks/mca.h> #include <amdblocks/msr_zen.h> -#include <amdblocks/reset.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> -#include <acpi/acpi.h> #include <console/console.h> -#include <arch/bert_storage.h> -#include <cper.h> #include <types.h> -/* MISC4 is the last used register in the MCAX banks of Picasso */ -#define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1) - -struct mca_bank_status { - unsigned int bank; - msr_t sts; -}; - -static inline size_t mca_report_size_reqd(void) -{ - size_t size; - - size = sizeof(acpi_generic_error_status_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_proc_generic_error_section_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_ia32x64_proc_error_section_t); - - /* Check Error */ - size += cper_ia32x64_check_sz(); - - /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); - - /* Context of CTL, STATUS, ADDR, MISC0, CONFIG, IPID, SYND, RESERVED, DESTAT, DEADDR, - MISC1, MISC2, MISC3, MISC4 */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, MCAX_USED_REGISTERS_PER_BANK); - - /* Context of CTL_MASK */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); - - return size; -} - -static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) -{ - int error = mca_err_type(mci->sts); - - if (error == MCA_ERRTYPE_BUS) - return X86_PROCESSOR_BUS_CHK; - if (error == MCA_ERRTYPE_INT) - return X86_PROCESSOR_MS_CHK; - if (error == MCA_ERRTYPE_MEM) - return X86_PROCESSOR_CACHE_CHK; - if (error == MCA_ERRTYPE_TLB) - return X86_PROCESSOR_TLB_CHK; - - return X86_PROCESSOR_MS_CHK; /* unrecognized */ -} - -/* Fill additional information in the Generic Processor Error Section. */ -static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank_status *mci) -{ - int type = mca_err_type(mci->sts); - - if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ - sec->error_type = GENPROC_ERRTYPE_BUS; - else if (type == MCA_ERRTYPE_INT) - sec->error_type = GENPROC_ERRTYPE_UARCH; - else if (type == MCA_ERRTYPE_MEM) - sec->error_type = GENPROC_ERRTYPE_CACHE; - else if (type == MCA_ERRTYPE_TLB) - sec->error_type = GENPROC_ERRTYPE_TLB; - else - sec->error_type = GENPROC_ERRTYPE_UNKNOWN; - sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; -} - -/* Convert an error reported by an MCA bank into BERT information to be reported - * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, - * which is the best method to report MSR context. As a result, add two - * structures: A "processor generic error" that is parsed, and an IA32/X64 one - * to capture complete information. - */ -static void build_bert_mca_error(struct mca_bank_status *mci) -{ - acpi_generic_error_status_t *status; - acpi_hest_generic_data_v300_t *gen_entry; - acpi_hest_generic_data_v300_t *x86_entry; - cper_proc_generic_error_section_t *gen_sec; - cper_ia32x64_proc_error_section_t *x86_sec; - cper_ia32x64_proc_error_info_t *chk; - cper_ia32x64_context_t *ctx; - - if (mca_report_size_reqd() > bert_storage_remaining()) - goto failed; - - status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); - if (!status) - goto failed; - - gen_entry = acpi_hest_generic_data3(status); - gen_sec = section_of_acpientry(gen_sec, gen_entry); - - fill_generic_section(gen_sec, mci); - - x86_entry = bert_append_ia32x64(status); - x86_sec = section_of_acpientry(x86_sec, x86_entry); - - chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); - if (!chk) - goto failed; - - ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCAX_CTL_MSR(mci->bank), - MCAX_USED_REGISTERS_PER_BANK); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MCA_CTL_MASK_MSR(mci->bank), 1); - if (!ctx) - goto failed; - - return; - -failed: - /* We're here because of a hardware error, don't break something else */ - printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); -} - static const char *const mca_bank_name[] = { [0] = "Load-store unit", [1] = "Instruction fetch unit", diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index cf3f3ac..566f54c 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -5,136 +5,9 @@ #include <cpu/amd/msr.h> #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> -#include <acpi/acpi.h> #include <console/console.h> -#include <arch/bert_storage.h> -#include <cper.h> #include <types.h> -struct mca_bank_status { - unsigned int bank; - msr_t sts; -}; - -static inline size_t mca_report_size_reqd(void) -{ - size_t size; - - size = sizeof(acpi_generic_error_status_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_proc_generic_error_section_t); - - size += sizeof(acpi_hest_generic_data_v300_t); - size += sizeof(cper_ia32x64_proc_error_section_t); - - /* Check Error */ - size += cper_ia32x64_check_sz(); - - /* Context of MCG_CAP, MCG_STAT, MCG_CTL */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 3); - - /* Context of MCi_CTL, MCi_STATUS, MCi_ADDR, MCi_MISC */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 4); - - /* Context of CTL_MASK */ - size += cper_ia32x64_ctx_sz_bytype(CPER_IA32X64_CTX_MSR, 1); - - return size; -} - -static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci) -{ - int error = mca_err_type(mci->sts); - - if (error == MCA_ERRTYPE_BUS) - return X86_PROCESSOR_BUS_CHK; - if (error == MCA_ERRTYPE_INT) - return X86_PROCESSOR_MS_CHK; - if (error == MCA_ERRTYPE_MEM) - return X86_PROCESSOR_CACHE_CHK; - if (error == MCA_ERRTYPE_TLB) - return X86_PROCESSOR_TLB_CHK; - - return X86_PROCESSOR_MS_CHK; /* unrecognized */ -} - -/* Fill additional information in the Generic Processor Error Section. */ -static void fill_generic_section(cper_proc_generic_error_section_t *sec, - struct mca_bank_status *mci) -{ - int type = mca_err_type(mci->sts); - - if (type == MCA_ERRTYPE_BUS) /* try to map MCA errors to CPER types */ - sec->error_type = GENPROC_ERRTYPE_BUS; - else if (type == MCA_ERRTYPE_INT) - sec->error_type = GENPROC_ERRTYPE_UARCH; - else if (type == MCA_ERRTYPE_MEM) - sec->error_type = GENPROC_ERRTYPE_CACHE; - else if (type == MCA_ERRTYPE_TLB) - sec->error_type = GENPROC_ERRTYPE_TLB; - else - sec->error_type = GENPROC_ERRTYPE_UNKNOWN; - sec->validation |= GENPROC_VALID_PROC_ERR_TYPE; -} - -/* Convert an error reported by an MCA bank into BERT information to be reported - * by the OS. The ACPI driver doesn't recognize/parse the IA32/X64 structure, - * which is the best method to report MSR context. As a result, add two - * structures: A "processor generic error" that is parsed, and an IA32/X64 one - * to capture complete information. - * - * Future work may attempt to interpret the specific Family 15h error symptoms - * found in the MCA registers. This data could enhance the reporting of the - * Processor Generic section and the failing error/check added to the - * IA32/X64 section. - */ -static void build_bert_mca_error(struct mca_bank_status *mci) -{ - acpi_generic_error_status_t *status; - acpi_hest_generic_data_v300_t *gen_entry; - acpi_hest_generic_data_v300_t *x86_entry; - cper_proc_generic_error_section_t *gen_sec; - cper_ia32x64_proc_error_section_t *x86_sec; - cper_ia32x64_proc_error_info_t *chk; - cper_ia32x64_context_t *ctx; - - if (mca_report_size_reqd() > bert_storage_remaining()) - goto failed; - - status = bert_new_event(&CPER_SEC_PROC_GENERIC_GUID); - if (!status) - goto failed; - - gen_entry = acpi_hest_generic_data3(status); - gen_sec = section_of_acpientry(gen_sec, gen_entry); - - fill_generic_section(gen_sec, mci); - - x86_entry = bert_append_ia32x64(status); - x86_sec = section_of_acpientry(x86_sec, x86_entry); - - chk = new_cper_ia32x64_check(status, x86_sec, error_to_chktype(mci)); - if (!chk) - goto failed; - - ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MCG_CAP, 3); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, IA32_MC_CTL(mci->bank), 4); - if (!ctx) - goto failed; - ctx = cper_new_ia32x64_context_msr(status, x86_sec, MC_CTL_MASK(mci->bank), 1); - if (!ctx) - goto failed; - - return; - -failed: - /* We're here because of a hardware error, don't break something else */ - printk(BIOS_ERR, "Error: Not enough room in BERT region for Machine Check error\n"); -} - static const char *const mca_bank_name[] = { [0] = "Load-store unit", [1] = "Instruction fetch unit", -- To view, visit https://review.coreboot.org/c/coreboot/+/56283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Gerrit-Change-Number: 56283 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header
by Martin Roth (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Michał Żygowski, Marshall Dawson, Nikolai Vyssotski, Andrey Petrov, Patrick Rudolph, Nathaniel L Desimone. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56190 ) Change subject: src/drivers/intel/fsp2_0: allow larger FSP 2.0 header ...................................................................... Patch Set 5: (2 comments) File src/drivers/intel/fsp2_0/util.c: https://review.coreboot.org/c/coreboot/+/56190/comment/82204001_b402c6ca PS5, Line 17: if (CONFIG(PLATFORM_USES_FSP2_2)) Somewhat unrelated to this patch, but does it make sense to switch this from a config to a runtime option? I could see this being a problem if at some point in the future, we updated a platform's FSP version. Say 6 months from now, we decided to update the Cezanne FSP from 2.0 to 2.2. Or should we just not worry about that? Either way, I think that's for a future patch if we do decide to change it. https://review.coreboot.org/c/coreboot/+/56190/comment/fb0ee6f4_30ea485a PS5, Line 30: Should we check the bytes 10 & 11 as well? If we're not changing the version at runtime, Byte 10 should directly match the FSP version config in BCD. For Byte 11 I'd expect that FSP 2.2 would use header version 5, 2.1 would be 4, and 2.0 would use header version 3. I'd be good with this being done in a follow-on patch as well if we decide to do it. -- To view, visit https://review.coreboot.org/c/coreboot/+/56190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8422447b2cff0a6c536e13014905ffa15c70586 Gerrit-Change-Number: 56190 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 16:31:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56339 to look at the new patch set (#9). Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... asrock/e3c246d4i: Add Intel Coffee Lake board This board has upstream OpenBMC support so it's quite nice to develop on (with some extra patches to enable access to the host flash). This board very loosely used the prodrive/hermes and system76/oryp5 as a base and inspiration. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running Option ROMs of the 10G NICs. TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/gpio.h A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 12 files changed, 1,555 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Configure the SKU specific parameters for VR dom...
by Vinay Kumar (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Furquan Shaikh, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Kane Chen, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili. Vinay Kumar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56325 ) Change subject: soc/intel/alderlake: Configure the SKU specific parameters for VR domains ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/vr_config.c: https://review.coreboot.org/c/coreboot/+/56325/comment/c9ff44dc_0287b53b PS7, Line 75: { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, : }; > these settings look so different than the setting in fsp mCpuVrOverrideTable […] not from vrtt report. but these settings are according to iPDS PowerMap for ADLP. -- To view, visit https://review.coreboot.org/c/coreboot/+/56325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Gerrit-Change-Number: 56325 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 16:06:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: add pcie modphy settings
by Jamie Chen (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jamie Chen, Kane Chen, Patrick Rudolph. Hello build bot (Jenkins), Jamie Chen, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56336 to look at the new patch set (#3). Change subject: soc/intel/jasperlake: add pcie modphy settings ...................................................................... soc/intel/jasperlake: add pcie modphy settings This patch adds device tree settings to control pcie modphy tuning FSP UPDs. With this patch, the pcie modphy can be tuned per board. BUG=b:192716633 BRANCH=NONE TEST=build dedede variant coreboot with fw_debug enable and check if these settings have been changed successfully on fsp debug log. Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/romstage/fsp_params.c 2 files changed, 61 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/56336/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Gerrit-Change-Number: 56336 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Configure the SKU specific parameters for VR dom...
by Kane Chen (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Furquan Shaikh, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Balaji Manigandan, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56325 ) Change subject: soc/intel/alderlake: Configure the SKU specific parameters for VR domains ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/vr_config.c: https://review.coreboot.org/c/coreboot/+/56325/comment/f954ae2f_852771ce PS7, Line 75: { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, : { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, : }; these settings look so different than the setting in fsp mCpuVrOverrideTable may i learn where it from? from vrtt report? -- To view, visit https://review.coreboot.org/c/coreboot/+/56325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Gerrit-Change-Number: 56325 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 15:53:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL
by Sridhar Siricilla (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Ronak Kanabar, Patrick Rudolph, Baieswara Reddy Sagili. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56176 ) Change subject: soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/56176/comment/ae029ff6_0043c5c1 PS6, Line 610: VccInAuxImonIccImax How about allowing the VccInAuxImonIccImax config from Device tree? -- To view, visit https://review.coreboot.org/c/coreboot/+/56176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Gerrit-Change-Number: 56176 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 15:48:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/brya: Enable south XHCI ports 1 and 2"
by EricR Lai (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Ronak Kanabar. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56132 ) Change subject: Revert "mb/google/brya: Enable south XHCI ports 1 and 2" ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > There has got to be some way to fix Gerrit to add that automatically .... bug of website haha.. -- To view, visit https://review.coreboot.org/c/coreboot/+/56132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82bae21d185247bc0f3580fd6f92abb8eece6732 Gerrit-Change-Number: 56132 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 15:40:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by Julian Schroeder (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Julian Schroeder has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56188 ) Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56188/comment/314e7773_20f21d1a PS6, Line 11: > Can you add two lines (plus another blank line) […] Done Patchset: PS6: updated commit msg with bug number -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 6 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 15:33:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add ACPI CPPC support for AMD
by Julian Schroeder (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Julian Schroeder. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56188 to look at the new patch set (#7). Change subject: soc/amd/cezanne: add ACPI CPPC support for AMD ...................................................................... soc/amd/cezanne: add ACPI CPPC support for AMD This leverages the existing Collaborative Processor Performance Control (CPPC) support and adds CPPC init for AMD/Cezanne. BUG=b:185814875 TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/acpi.c A src/soc/amd/cezanne/cppc.c A src/soc/amd/cezanne/include/soc/cppc.h M src/soc/amd/cezanne/include/soc/msr.h 5 files changed, 215 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/56188/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Gerrit-Change-Number: 56188 Gerrit-PatchSet: 7 Gerrit-Owner: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021