coreboot-gerrit July 2021

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Change in coreboot[master]: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56298 ) Change subject: soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs ...................................................................... soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and SOC_INTEL_CRASHLOG is selected by the SoC user. Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56298 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index f9b3d60..b32831e 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -305,10 +305,8 @@ m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; /* CrashLog config */ - if (CONFIG(SOC_INTEL_CRASHLOG)) { - m_cfg->CpuCrashLogDevice = 1; - m_cfg->CpuCrashLogEnable = 1; - } + m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); + m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; } static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/56298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80 Gerrit-Change-Number: 56298 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Disable xDCI in devicetree
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52262 ) Change subject: mb/intel/adlrvp: Disable xDCI in devicetree ...................................................................... mb/intel/adlrvp: Disable xDCI in devicetree Disable tcss_xdci as it is not used. Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52262 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 8c823cd..65dc9ca 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -335,7 +335,6 @@ device ref tbt_pcie_rp3 on end device ref crashlog off end device ref tcss_xhci on end - device ref tcss_xdci on end device ref tcss_dma0 on end device ref tcss_dma1 on end device ref xhci on -- To view, visit https://review.coreboot.org/c/coreboot/+/52262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94102240b13d2b96e0295f41bc2b0ba078faf342 Gerrit-Change-Number: 52262 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Archana Patni <archana.patni(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: monika.a(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default
by Patrick Georgi (Code Review) 15 Jul '21

15 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56289 ) Change subject: mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default ...................................................................... mb/google/guybrush: Make VBOOT_STARTS_BEFORE_BOOTBLOCK a default To be able to enable & disable PSP_verstage in the saved .config file, the symbol VBOOT_STARTS_BEFORE_BOOTBLOCK needs to be changed from a select to a default with a prompt. BUG=182477057 TEST=Build, get PSP_verstage, disable VBOOT_STARTS_BEFORE_BOOTBLOCK, verify that VBOOT_STARTS_IN_BOOTBLOCK is set. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56289 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 8 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index f9c577a..b57fc62 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -48,7 +48,14 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_SEPARATE_VERSTAGE - select VBOOT_STARTS_BEFORE_BOOTBLOCK + +config VBOOT_STARTS_BEFORE_BOOTBLOCK + bool "Enable PSP_verstage" + default y if VBOOT + +config VBOOT_STARTS_IN_BOOTBLOCK + bool + default y if VBOOT && !VBOOT_STARTS_BEFORE_BOOTBLOCK config VBOOT_STARTS_IN_BOOTBLOCK select NO_EARLY_BOOTBLOCK_POSTCODES -- To view, visit https://review.coreboot.org/c/coreboot/+/56289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba735f33f9b079c9868ef2fff099c5298ff72b6a Gerrit-Change-Number: 56289 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Angel Pons. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56339 to look at the new patch set (#7). Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... asrock/e3c246d4i: Add Intel Coffee Lake board This board has upstream OpenBMC support so it's quite nice to develop on (with some extra patches to enable access to the host flash). This board very loosely used the prodrive/hermes and system76/oryp5 as a base and inspiration. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running Option ROMs of the 10G NICs. TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,547 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... Patch Set 6: (17 comments) File src/mainboard/asrock/e3c246d4i/Kconfig: https://review.coreboot.org/c/coreboot/+/56339/comment/ee5491a9_2b820ecc PS4, Line 22: e3c246d4i > Shouldn't this be uppercase? E3C246D4I Done https://review.coreboot.org/c/coreboot/+/56339/comment/2bf24c51_a7f87bbf PS4, Line 36: Hardware COM1 port > Everything is hardware. […] Done File src/mainboard/asrock/e3c246d4i/Kconfig.name: https://review.coreboot.org/c/coreboot/+/56339/comment/141d11f9_3b6355ba PS4, Line 2: e3c246d4i > Same, E3C246D4I Done File src/mainboard/asrock/e3c246d4i/Makefile.inc: https://review.coreboot.org/c/coreboot/+/56339/comment/d66b73bf_3fa82d75 PS4, Line 1: CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include > Copy-pasta? Done File src/mainboard/asrock/e3c246d4i/bootblock.c: https://review.coreboot.org/c/coreboot/+/56339/comment/8714da19_3d8b387e PS4, Line 19: 4 > 3? Done https://review.coreboot.org/c/coreboot/+/56339/comment/6e010b60_9b090721 PS4, Line 22: return AST2400_SUART1; > This path should never be reached, as it means something is very wrong with the Kconfig setting. […] Done File src/mainboard/asrock/e3c246d4i/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56339/comment/fd97b2cb_3ff773c7 PS2, Line 47: device pci 12.0 on end # Thermal Subsystem > I always align the comments with tabs. Done File src/mainboard/asrock/e3c246d4i/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56339/comment/eb1627c0_d0b3c592 PS4, Line 7: # Power limit > Dead comment Done https://review.coreboot.org/c/coreboot/+/56339/comment/b7903bdd_4158ba61 PS4, Line 14: # Serial IRQ Continuous > Redundant comment, drop? Done https://review.coreboot.org/c/coreboot/+/56339/comment/b8507e5d_2095c2b2 PS4, Line 93: device pci 17.0 on # SATA > Enable SATA power optimizer too? […] Done https://review.coreboot.org/c/coreboot/+/56339/comment/80ab6a1a_3d257676 PS4, Line 94: register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : register "SataPortsEnable[4]" = "1" : register "SataPortsEnable[5]" = "1" : register "SataPortsEnable[6]" = "1" : register "SataPortsEnable[7]" = "1" > Use an array initialiser for brevity's sake? […] Done https://review.coreboot.org/c/coreboot/+/56339/comment/99753030_945c351b PS4, Line 107: device pci 1b.0 on # PCI Express Port 17 > What is this used for? Avoiding coalescing? > > There's two OcuLink connectors and a M.2 slot. That's what the vendor does. It looks like FSP automatically disables it and does coalescing regardless of it being on here... File src/mainboard/asrock/e3c246d4i/dsdt.asl: https://review.coreboot.org/c/coreboot/+/56339/comment/44aa6706_f6b844de PS4, Line 10: // OEM revision > Is it, though? Done File src/mainboard/asrock/e3c246d4i/gpio.c: https://review.coreboot.org/c/coreboot/+/56339/comment/64cea08e_b8b717d5 PS4, Line 16: /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ > Comments should be trimmed '/* Pad configuration was generated automatically using intelp2m utility */'. What should be trimmed from the comments? File src/mainboard/asrock/e3c246d4i/romstage.c: https://review.coreboot.org/c/coreboot/+/56339/comment/92dcf0ef_14616444 PS4, Line 7: esthetic > *a*esthetic […] Done https://review.coreboot.org/c/coreboot/+/56339/comment/3394d2c5_b31eca6b PS4, Line 19: 0xa8 > Is this really 0xa8? I'd expect it to be 0xa6 (or even better, `0x53 << 1`) Done https://review.coreboot.org/c/coreboot/+/56339/comment/5b989b8a_1f7fea7a PS4, Line 26: 50 > Out of curiosity, where does this 50 come from? system76/oryp5. I have no idea what it should be... Any suggestions? -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 15 Jul 2021 14:00:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Angel Pons (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... Patch Set 4: (18 comments) Patchset: PS4: https://i.imgur.com/HZS8mwc.png File src/mainboard/asrock/e3c246d4i/Kconfig: https://review.coreboot.org/c/coreboot/+/56339/comment/36b7bec4_3e695800 PS4, Line 22: e3c246d4i Shouldn't this be uppercase? E3C246D4I https://review.coreboot.org/c/coreboot/+/56339/comment/3ce6b337_1bb745bf PS4, Line 36: Hardware COM1 port Everything is hardware. Do you mean the *physical* RS232 connector labelled COM1? File src/mainboard/asrock/e3c246d4i/Kconfig.name: https://review.coreboot.org/c/coreboot/+/56339/comment/a5386d73_54fa06b0 PS4, Line 2: e3c246d4i Same, E3C246D4I File src/mainboard/asrock/e3c246d4i/Makefile.inc: https://review.coreboot.org/c/coreboot/+/56339/comment/ed73ded0_d5fcb26e PS4, Line 1: CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include Copy-pasta? File src/mainboard/asrock/e3c246d4i/bootblock.c: https://review.coreboot.org/c/coreboot/+/56339/comment/cab63d9e_fc0f6ee1 PS4, Line 19: 4 3? https://review.coreboot.org/c/coreboot/+/56339/comment/bfa5524f_be0107c8 PS4, Line 22: return AST2400_SUART1; This path should never be reached, as it means something is very wrong with the Kconfig setting. How about: return dead_code_t(uint8_t); If this always causes build errors (even for valid values), try dropping the `com` parameter and using `CONFIG_UART_FOR_CONSOLE` directly in the switch statement. File src/mainboard/asrock/e3c246d4i/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56339/comment/5a754b5d_1eff1f5f PS2, Line 47: device pci 12.0 on end # Thermal Subsystem > Should the comments be aligned? I always align the comments with tabs. File src/mainboard/asrock/e3c246d4i/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56339/comment/1dd109f5_01f06be7 PS4, Line 7: # Power limit Dead comment https://review.coreboot.org/c/coreboot/+/56339/comment/ac7bf8af_0bc24b1b PS4, Line 14: # Serial IRQ Continuous Redundant comment, drop? https://review.coreboot.org/c/coreboot/+/56339/comment/b5ba461b_bc9301a6 PS4, Line 93: device pci 17.0 on # SATA Enable SATA power optimizer too? register "satapwroptimize" = "1" https://review.coreboot.org/c/coreboot/+/56339/comment/488ffd28_775dff75 PS4, Line 94: register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : register "SataPortsEnable[4]" = "1" : register "SataPortsEnable[5]" = "1" : register "SataPortsEnable[6]" = "1" : register "SataPortsEnable[7]" = "1" Use an array initialiser for brevity's sake? register "SataPortsEnable" = "{ [0] = 1, [1] = 1, [2] = 1, [3] = 1, [4] = 1, [5] = 1, [6] = 1, [7] = 1, }" https://review.coreboot.org/c/coreboot/+/56339/comment/5b82fcb1_3da403d3 PS4, Line 107: device pci 1b.0 on # PCI Express Port 17 What is this used for? Avoiding coalescing? There's two OcuLink connectors and a M.2 slot. File src/mainboard/asrock/e3c246d4i/dsdt.asl: https://review.coreboot.org/c/coreboot/+/56339/comment/d3e2900b_4ef8812e PS4, Line 10: // OEM revision Is it, though? File src/mainboard/asrock/e3c246d4i/gpio.c: https://review.coreboot.org/c/coreboot/+/56339/comment/984449d3_66011ece PS4, Line 16: /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ Comments should be trimmed File src/mainboard/asrock/e3c246d4i/romstage.c: https://review.coreboot.org/c/coreboot/+/56339/comment/776efcd3_b16e32af PS4, Line 7: esthetic *a*esthetic Personally, I'd rather put this information in a documentation page. https://review.coreboot.org/c/coreboot/+/56339/comment/a33a69e0_3a9e5b04 PS4, Line 19: 0xa8 Is this really 0xa8? I'd expect it to be 0xa6 (or even better, `0x53 << 1`) https://review.coreboot.org/c/coreboot/+/56339/comment/74f2a540_ac015fc6 PS4, Line 26: 50 Out of curiosity, where does this 50 come from? -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jul 2021 13:36:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56339 to look at the new patch set (#6). Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... asrock/e3c246d4i: Add Intel Coffee Lake board This board has upstream OpenBMC support so it's quite nice to develop on (with some extra patches to enable access to the host flash). This board very loosely used the prodrive/hermes and system76/oryp5 as a base and inspiration. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running Option ROMs of the 10G NICs. TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,554 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asrock/e3c246d4i: Add Intel Coffee Lake board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56339 to look at the new patch set (#5). Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ...................................................................... asrock/e3c246d4i: Add Intel Coffee Lake board This board has upstream OpenBMC support so it's quite nice to develop on (with some extra patches to enable access to the host flash). This board very loosely used the prodrive/hermes and system76/oryp5 as a base and inspiration. What is tested: - ast2500 BMC: video, serial - 10G NIC - USB boot: from virtual CD from BMC and real disk - EDK2 with UefiPayloadPkg - 8G DIMM in slot0 What does not work: - SeaBIOS: seems to hang in the menu. Possibly related to running Option ROMs of the 10G NICs. TODO: A lot of things are pretty bare in this port like USB and PCIe setup, but I don't own schematics so it's hard to improve on that. No idea what the nuvoton superio is hooked up to either. Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/e3c246d4i/Kconfig A src/mainboard/asrock/e3c246d4i/Kconfig.name A src/mainboard/asrock/e3c246d4i/Makefile.inc A src/mainboard/asrock/e3c246d4i/board_info.txt A src/mainboard/asrock/e3c246d4i/bootblock.c A src/mainboard/asrock/e3c246d4i/devicetree.cb A src/mainboard/asrock/e3c246d4i/dsdt.asl A src/mainboard/asrock/e3c246d4i/gpio.c A src/mainboard/asrock/e3c246d4i/include/mainboard/gpio.h A src/mainboard/asrock/e3c246d4i/ramstage.c A src/mainboard/asrock/e3c246d4i/romstage.c 11 files changed, 1,555 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/56339/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: asrock/e3c246d4i: Add board
by Arthur Heymans (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 ) Change subject: asrock/e3c246d4i: Add board ...................................................................... Patch Set 4: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/56339/comment/960bfc34_5fd4ecd6 PS2, Line 7: asrock/e3c246d4i: Add board > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/56339/comment/acf6f43c_8dbe7fa4 PS2, Line 9: Openbmc > OpenBMC Done https://review.coreboot.org/c/coreboot/+/56339/comment/511ada78_c61755f3 PS2, Line 11: > It’d be great if you could document if you wrote this from scratch or used some other board as templ […] Done https://review.coreboot.org/c/coreboot/+/56339/comment/d8dde708_40a41f6d PS2, Line 21: options > Option ROM? Done File src/mainboard/asrock/e3c246d4i/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56339/comment/288da789_f4e27a53 PS2, Line 47: device pci 12.0 on end # Thermal Subsystem > Should the comments be aligned? Done File src/mainboard/asrock/e3c246d4i/dsdt.asl: https://review.coreboot.org/c/coreboot/+/56339/comment/106f194a_28e65138 PS2, Line 27: > Please remove the blank line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66e168c8af5de9862b0724fa397ecd709843af1a Gerrit-Change-Number: 56339 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 13:26:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: add pcie modphy settings
by Jamie Chen (Code Review) 15 Jul '21

15 Jul '21

Attention is currently required from: Jamie Chen, Kane Chen, Patrick Rudolph. Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56336 ) Change subject: soc/intel/jasperlake: add pcie modphy settings ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56336/comment/89acaeee_d41b32cd PS1, Line 9: This patch expose some pcie modphy UPDs/configuration : to be filled from devicetree. It's for fine tune pcie : port signal quality. > This patch adds device tree settings to control pcie modphy tuning FSP UPDS. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831 Gerrit-Change-Number: 56336 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 15 Jul 2021 13:20:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2021