coreboot-gerrit May 2021

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Change in coreboot[master]: inteltool: add initial support for Emmits Burg PCH
by Jonathan Zhang (Code Review) 03 May '21

03 May '21

Attention is currently required from: Stefan Reinauer. Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52864 ) Change subject: inteltool: add initial support for Emmits Burg PCH ...................................................................... inteltool: add initial support for Emmits Burg PCH Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I6a4027bf51b3a189e64211e77621b3dd6c80b00d --- M util/inteltool/inteltool.c M util/… [View More]

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Change in coreboot[master]: inteltool: add initial suppot for Sapphire Rapids Scalable Processor
by Jonathan Zhang (Code Review) 03 May '21

03 May '21

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52863 ) Change subject: inteltool: add initial suppot for Sapphire Rapids Scalable Processor ...................................................................... inteltool: add initial suppot for Sapphire Rapids Scalable Processor Intel Sapphire Rapids Scalable Processor is a 4th generation processor of Intel Xeon Scalable Processor family. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com… [View More]

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Change in coreboot[master]: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED
by Martin Roth (Code Review) 03 May '21

03 May '21

Martin Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52763 ) Change subject: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/52763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: … [View More]

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Change in coreboot[master]: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Shaunak Saha, Furquan Shaikh, Martin Roth, Angel Pons, Subrata Banik, Michael Niewöhner, Patrick Rudolph. Hello build bot (Jenkins), Shaunak Saha, Patrick Georgi, Martin Roth, Furquan Shaikh, Angel Pons, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51649 to look at the new patch set (#22). Change subject: soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads ...… [View More]................................................................... soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb M src/mainboard/google/volteer/variants/elemi/overridetree.cb M src/mainboard/google/volteer/variants/lindar/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/voema/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c A src/soc/intel/tigerlake/include/soc/tcss.h 13 files changed, 87 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/51649/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/51649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Gerrit-Change-Number: 51649 Gerrit-PatchSet: 22 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset [View Less]

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Change in coreboot[master]: soc/intel/tigerlake: Add known GPIO virtual wire information
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52589 to look at the new patch set (#6). Change subject: soc/intel/tigerlake: Add known GPIO virtual wire information ...................................................................... soc/intel/tigerlake: Add known GPIO virtual wire information GPIO communities … [View More]

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Change in coreboot[master]: soc/intel/common: Add virtual wire mapping entries to GPIO communities
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52588 to look at the new patch set (#4). Change subject: soc/intel/common: Add virtual wire mapping entries to GPIO communities ...................................................................... soc/intel/common: Add virtual wire mapping entries to GPIO … [View More]

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Change in coreboot[master]: soc/intel/common: Add CPU Port ID field to GPIO communities
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52590 to look at the new patch set (#4). Change subject: soc/intel/common: Add CPU Port ID field to GPIO communities ...................................................................... soc/intel/common: Add CPU Port ID field to GPIO communities The CPU can have … [View More]

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Change in coreboot[master]: soc/intel/cannonlake: Simplify FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52842 ) Change subject: soc/intel/cannonlake: Simplify FSP chipset lockdown configuration ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/52842/comment/0d59206a_077d1926 PS3, Line 479: uint8_t &… [View More]

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Change in coreboot[master]: soc/intel/tigerlake: Simplify FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52844 ) Change subject: soc/intel/tigerlake: Simplify FSP chipset lockdown configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/tigerlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/52844/comment/fe131bf5_f60355cc PS5, Line 205: uint8_t … [View More]

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Change in coreboot[master]: soc/intel/jasperlake: Simplify FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52845 ) Change subject: soc/intel/jasperlake: Simplify FSP chipset lockdown configuration ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/52845/comment/3ffe8a00_5cc946f6 PS5, Line 106: uint8_t &… [View More]

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coreboot-gerrit May 2021