coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS
by Martin Roth (Code Review) 03 May '21

03 May '21

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52867 ) Change subject: drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS ...................................................................... drivers/intel/fsp2_0: Add timestamps for loading FSPM & FSPS The loads of the FSPM and FSPS binaries are not insignificant amounts of time, and without these timestamps, it's not clear what's going on in those time blocks. For FSPM, the timestamps can run together to make it look like that time is still part of the romstage init time. BUG=None TEST=Build & Boot guybrush, look at timestamps. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/52867/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index a572150..f202fbb 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -119,6 +119,8 @@ TS_FSP_AFTER_END_OF_FIRMWARE = 961, TS_FSP_MULTI_PHASE_SI_INIT_START = 962, TS_FSP_MULTI_PHASE_SI_INIT_END = 963, + TS_FSP_INITRAM_LOAD = 970, + TS_FSP_SILICON_INIT_LOAD = 971, /* 1000+ reserved for payloads (1000-1200: ChromeOS depthcharge) */ @@ -261,6 +263,10 @@ { TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" }, { TS_FSP_AFTER_END_OF_FIRMWARE, "returning from FspNotify(EndOfFirmware)" }, + + { TS_FSP_INITRAM_LOAD, "Loading FSP-M" }, + { TS_FSP_SILICON_INIT_LOAD, "Loading FSP-S" }, + { TS_START_POSTCAR, "start of postcar" }, { TS_END_POSTCAR, "end of postcar" }, }; diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index c5d560a..1d48973 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -387,6 +387,7 @@ _car_unallocated_start - _car_region_start, 0); memranges_insert(memmap, (uintptr_t)_program, REGION_SIZE(program), 0); + timestamp_add_now(TS_FSP_INITRAM_LOAD); if (fsp_load_component(&fspld, hdr) != CB_SUCCESS) die("FSPM not available or failed to load!\n"); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 707a380..625451b 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -228,6 +228,7 @@ void fsp_silicon_init(void) { + timestamp_add_now(TS_FSP_SILICON_INIT_LOAD); fsps_load(); mb_pre_fsps_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/52867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5796d4cdd512799c2eafee45a8ef561de5258b91 Gerrit-Change-Number: 52867 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add mb hooks before & after FSP calls
by Martin Roth (Code Review) 03 May '21

03 May '21

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52866 ) Change subject: drivers/intel/fsp2_0: Add mb hooks before & after FSP calls ...................................................................... drivers/intel/fsp2_0: Add mb hooks before & after FSP calls There are currently various callbacks and hooks for chipsets and mainboards in various places around the FSP calls, but I need some mainboard hooks immediately before and after the FSP calls. This allows for GPIO initialization before the calls as required and easy analysis and updates of register changes within the FSP. BUG=None TEST=Build & Boot guybrush with following patches Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I8dc6eb95fa8a1114234cfd7467507992c25669f1 --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c 3 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/52866/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 8561600..3450050 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -71,6 +71,15 @@ struct mma_config_param *mma_cfg); /* + * Weak functions before and after FSP-M and FSP-S calls for use by mainboards. + * These can save and restore registers, print values, or do other initialization. + */ +void mb_pre_fspm_init(void); +void mb_post_fspm_init(void); +void mb_pre_fsps_init(void); +void mb_post_fsps_init(void); + +/* * As per FSP integration guide: * If bootloader needs to take control of APs back, a full AP re-initialization is * required after FSP-S is completed and control has been transferred back to bootloader diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index bbc26bc..c5d560a 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -195,6 +195,14 @@ return 0; } +__weak void mb_pre_fspm_init(void) +{ +} + +__weak void mb_post_fspm_init(void) +{ +} + /* * Allow SoC and/or mainboard to bump the revision of the FSP setting * number. The FSP spec uses the low 8 bits as the build number. Take over @@ -386,9 +394,12 @@ die("FSPM XIP base does not match: %p vs %p\n", (void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog)); + mb_pre_fspm_init(); timestamp_add_now(TS_BEFORE_INITRAM); do_fsp_memory_init(&context, s3wake); timestamp_add_now(TS_AFTER_INITRAM); + mb_post_fspm_init(); + } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 53c9626..707a380 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -34,6 +34,14 @@ return 1; } +__weak void mb_pre_fsps_init(void) +{ +} + +__weak void mb_post_fsps_init(void) +{ +} + /* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2 * has multiple stages as below. */ @@ -221,7 +229,10 @@ void fsp_silicon_init(void) { fsps_load(); + + mb_pre_fsps_init(); do_silicon_init(&fsps_hdr); + mb_post_fsps_init(); } __weak void soc_load_logo(FSPS_UPD *supd) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/52866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dc6eb95fa8a1114234cfd7467507992c25669f1 Gerrit-Change-Number: 52866 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: add qclib support
by Shelley Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Ravi kumar, Martin Roth, mturney mturney, Julius Werner, Sudheer Amrabadi. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50582 ) Change subject: sc7280: add qclib support ...................................................................... Patch Set 32: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Gerrit-Change-Number: 50582 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Comment-Date: Mon, 03 May 2021 21:37:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: Enable macronix SPI config
by Shelley Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Ravi kumar, Sajida Bhanu, mturney mturney, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50583 ) Change subject: herobrine: Enable macronix SPI config ...................................................................... Patch Set 32: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Gerrit-Change-Number: 50583 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 03 May 2021 21:36:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: acpi: add Generic Initiator Affinity structure for SRAT
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Lance Zhao, Jonathan Zhang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52734 ) Change subject: acpi: add Generic Initiator Affinity structure for SRAT ...................................................................... Patch Set 1: (6 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/52734/comment/5a1a4a63_26b9de41 PS1, Line 512: ; remove this https://review.coreboot.org/c/coreboot/+/52734/comment/43519daa_02c07ff2 PS1, Line 512: u16 seg, u8 bus, u8 dev, u8 func, u32 flags); align this with the previous line https://review.coreboot.org/c/coreboot/+/52734/comment/3089c3df_ff36f620 PS1, Line 514: 5; /* Generic Initiator Affinity structure */ : gia->length = sizeof(acpi_srat_gia_t); enums or #defines would be nice here instead of magic numbers https://review.coreboot.org/c/coreboot/+/52734/comment/be7b687f_75065083 PS1, Line 517: 1; /* PCIe device handle */ enums or #defines would be nice here instead of magic numbers https://review.coreboot.org/c/coreboot/+/52734/comment/30934b86_e34b8532 PS1, Line 521: (((dev) & 0x1F) << 3) `PCI_SLOT(dev)` https://review.coreboot.org/c/coreboot/+/52734/comment/47d610dd_61b267cc PS1, Line 521: ((func) & 0x07) `PCI_FUNC(func)` -- To view, visit https://review.coreboot.org/c/coreboot/+/52734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6ef01c59e02f30dc290f27e741027e16f5d8359 Gerrit-Change-Number: 52734 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Comment-Date: Mon, 03 May 2021 21:35:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: add qclib support
by Shelley Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Ravi kumar, Martin Roth, mturney mturney, Julius Werner, Sudheer Amrabadi. Shelley Chen has uploaded a new patch set (#32) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50582 ) Change subject: sc7280: add qclib support ...................................................................... sc7280: add qclib support BUG=b:182963902 Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50582/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/50582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Gerrit-Change-Number: 50582 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/acpi: Add initial support for HMAT
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Stefan Reinauer, Angel Pons, Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52047 ) Change subject: src/acpi: Add initial support for HMAT ...................................................................... Patch Set 5: Code-Review+1 (2 comments) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/52047/comment/cc481616_7903fe84 PS5, Line 242: u8 min_transfer_size; this has a slightly odd definition, a comment may be helpful https://review.coreboot.org/c/coreboot/+/52047/comment/bdaed25b_43a14b50 PS5, Line 261: u32 cache_attributes Some `enum`s or `#define` values could be useful to describe this bitfield -- To view, visit https://review.coreboot.org/c/coreboot/+/52047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Gerrit-Change-Number: 52047 Gerrit-PatchSet: 5 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Mon, 03 May 2021 21:30:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
by Furquan Shaikh (Code Review) 03 May '21

03 May '21

Attention is currently required from: Bora Guvendik, Selma Bensaid, Maulik V Vaghela. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52865 ) Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52865/comment/0d20c15c_d644ec8f PS1, Line 9: We need to configure CPU PCIE root port related gpios in early : boot block stage for CPU root ports to work. Can you please add the reason why CPU root ports do not work if the pads are configured later on i.e. ramstage? -- To view, visit https://review.coreboot.org/c/coreboot/+/52865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Gerrit-Change-Number: 52865 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Mon, 03 May 2021 21:28:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
by Bora Guvendik (Code Review) 03 May '21

03 May '21

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52865 ) Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO ...................................................................... mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 --- M src/mainboard/intel/adlrvp/early_gpio_m.c 1 file changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/52865/1 diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index 116d3c6..3b60e24 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -11,6 +11,94 @@ PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* WWAN_PWR_EN */ PAD_CFG_GPO(GPP_A8, 1, DEEP), + + /* CPU PCIe VGPIO for RP0 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP1 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP2 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1), + + /* CPU PCIe vGPIO for RP3 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), }; static const struct pad_config early_uart_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099 Gerrit-Change-Number: 52865 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: herobrine: Enable macronix SPI config
by Shelley Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, Sajida Bhanu, mturney mturney, Julius Werner. Shelley Chen has uploaded a new patch set (#32) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50583 ) Change subject: herobrine: Enable macronix SPI config ...................................................................... herobrine: Enable macronix SPI config Enable macronix SPI config on herobrine board. BUG=b:182963902 Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/mainboard/google/herobrine/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/50583/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/50583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I505ee95d9f2ca16baf244135b3e2e8fe72f93491 Gerrit-Change-Number: 50583 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021