Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52866 )
Change subject: drivers/intel/fsp2_0: Add mb hooks before & after FSP calls
......................................................................
drivers/intel/fsp2_0: Add mb hooks before & after FSP calls
There are currently various callbacks and hooks for chipsets and
mainboards in various places around the FSP calls, but I need some
mainboard hooks immediately before and after the FSP calls.
This allows for GPIO initialization before the calls as required and
easy analysis and updates of register changes within the FSP.
BUG=None
TEST=Build & Boot guybrush with following patches
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I8dc6eb95fa8a1114234cfd7467507992c25669f1
---
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
3 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/52866/1
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 8561600..3450050 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -71,6 +71,15 @@
struct mma_config_param *mma_cfg);
/*
+ * Weak functions before and after FSP-M and FSP-S calls for use by mainboards.
+ * These can save and restore registers, print values, or do other initialization.
+ */
+void mb_pre_fspm_init(void);
+void mb_post_fspm_init(void);
+void mb_pre_fsps_init(void);
+void mb_post_fsps_init(void);
+
+/*
* As per FSP integration guide:
* If bootloader needs to take control of APs back, a full AP re-initialization is
* required after FSP-S is completed and control has been transferred back to bootloader
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index bbc26bc..c5d560a 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -195,6 +195,14 @@
return 0;
}
+__weak void mb_pre_fspm_init(void)
+{
+}
+
+__weak void mb_post_fspm_init(void)
+{
+}
+
/*
* Allow SoC and/or mainboard to bump the revision of the FSP setting
* number. The FSP spec uses the low 8 bits as the build number. Take over
@@ -386,9 +394,12 @@
die("FSPM XIP base does not match: %p vs %p\n",
(void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog));
+ mb_pre_fspm_init();
timestamp_add_now(TS_BEFORE_INITRAM);
do_fsp_memory_init(&context, s3wake);
timestamp_add_now(TS_AFTER_INITRAM);
+ mb_post_fspm_init();
+
}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 53c9626..707a380 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -34,6 +34,14 @@
return 1;
}
+__weak void mb_pre_fsps_init(void)
+{
+}
+
+__weak void mb_post_fsps_init(void)
+{
+}
+
/* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2
* has multiple stages as below.
*/
@@ -221,7 +229,10 @@
void fsp_silicon_init(void)
{
fsps_load();
+
+ mb_pre_fsps_init();
do_silicon_init(&fsps_hdr);
+ mb_post_fsps_init();
}
__weak void soc_load_logo(FSPS_UPD *supd) { }
--
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Change subject: sc7280: add qclib support
......................................................................
Patch Set 32: Code-Review+2
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Shelley Chen has uploaded a new patch set (#32) to the change originally created by Ravi kumar. ( https://review.coreboot.org/c/coreboot/+/50582 )
Change subject: sc7280: add qclib support
......................................................................
sc7280: add qclib support
BUG=b:182963902
Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
---
M src/soc/qualcomm/sc7280/Makefile.inc
1 file changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50582/32
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Change subject: src/acpi: Add initial support for HMAT
......................................................................
Patch Set 5: Code-Review+1
(2 comments)
File src/include/acpi/acpi.h:
https://review.coreboot.org/c/coreboot/+/52047/comment/cc481616_7903fe84
PS5, Line 242: u8 min_transfer_size;
this has a slightly odd definition, a comment may be helpful
https://review.coreboot.org/c/coreboot/+/52047/comment/bdaed25b_43a14b50
PS5, Line 261: u32 cache_attributes
Some `enum`s or `#define` values could be useful to describe this bitfield
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52865 )
Change subject: mb/intel/adlrvp_m: Program CPU PCIE RP GPIOs in early GPIO
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52865/comment/0d20c15c_d644ec8f
PS1, Line 9: We need to configure CPU PCIE root port related gpios in early
: boot block stage for CPU root ports to work.
Can you please add the reason why CPU root ports do not work if the pads are configured later on i.e. ramstage?
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Change subject: src/intel/xeon_sp: add hardware error support (HEST)
......................................................................
Patch Set 13:
(2 comments)
File src/soc/intel/xeon_sp/include/soc/hest.h:
https://review.coreboot.org/c/coreboot/+/52090/comment/00adefbb_74e70112
PS13, Line 18:
: typedef struct acpi_gen_regaddr1 {
: u8 space_id; /* Address space ID */
: u8 bit_width; /* Register size in bits */
: u8 bit_offset; /* Register bit offset */
: u8 access_size; /* Access size since ACPI 2.0c */
: u64 addr; /* Register address */
: } __packed acpi_addr64_t;
This is in `acpi.h` now CB:49286 😉
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/52090/comment/60455812_2f4b929b
PS13, Line 292: /* Reserve memory for Enhanced error logging */
: if (CONFIG(SOC_RAS_ELOG)) {
: base_kb = cbmem_top_addr >> 10;
: size_kb = CONFIG_ERROR_LOG_BUFFER_SIZE >> 10;
: LOG_MEM_RESOURCE("elog_sts_blk", dev, index, base_kb, size_kb);
: reserved_ram_resource(dev, index++, base_kb, size_kb);
: elog_addr = cbmem_top_addr;
: printk(BIOS_DEBUG, "%s elog_addr = %llx size = %x\n",
: __func__, elog_addr, CONFIG_ERROR_LOG_BUFFER_SIZE);
: }
:
If I understand what you're doing correctly (trying to reserve CONFIG_ERROR_LOG_BUFFER_SIZE >> 10 bytes worth of memory in cbmem? You need to account for this used memory in cbmem so it knows about it, `cbmem_add`
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