coreboot-gerrit May 2021

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Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Lance Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Martin Roth, Johnny Lin, Rocky Phagura, David Hendricks, Angel Pons, Morgan Jang, Patrick Rudolph, Tim Chu. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 ) Change subject: src/intel/xeon_sp: add hardware error support (HEST) ...................................................................... Patch Set 13: (2 comments) File src/soc/intel/xeon_sp/include/soc/hest.h: https://review.coreboot.org/c/coreboot/+/52090/comment/00adefbb_74e70112 PS13, Line 18: : typedef struct acpi_gen_regaddr1 { : u8 space_id; /* Address space ID */ : u8 bit_width; /* Register size in bits */ : u8 bit_offset; /* Register bit offset */ : u8 access_size; /* Access size since ACPI 2.0c */ : u64 addr; /* Register address */ : } __packed acpi_addr64_t; This is in `acpi.h` now CB:49286 😉 File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/52090/comment/60455812_2f4b929b PS13, Line 292: /* Reserve memory for Enhanced error logging */ : if (CONFIG(SOC_RAS_ELOG)) { : base_kb = cbmem_top_addr >> 10; : size_kb = CONFIG_ERROR_LOG_BUFFER_SIZE >> 10; : LOG_MEM_RESOURCE("elog_sts_blk", dev, index, base_kb, size_kb); : reserved_ram_resource(dev, index++, base_kb, size_kb); : elog_addr = cbmem_top_addr; : printk(BIOS_DEBUG, "%s elog_addr = %llx size = %x\n", : __func__, elog_addr, CONFIG_ERROR_LOG_BUFFER_SIZE); : } : If I understand what you're doing correctly (trying to reserve CONFIG_ERROR_LOG_BUFFER_SIZE >> 10 bytes worth of memory in cbmem? You need to account for this used memory in cbmem so it knows about it, `cbmem_add` -- To view, visit https://review.coreboot.org/c/coreboot/+/52090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Gerrit-Change-Number: 52090 Gerrit-PatchSet: 13 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rocky Phagura Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 03 May 2021 21:23:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: doc/relnotes/4.14: add Intel Xeon-SP support status change
by Jonathan Zhang (Code Review) 03 May '21

03 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Christian Walter, Stefan Reinauer, David Hendricks, Angel Pons, Subrata Banik, Ron Minnich. Hello build bot (Jenkins), Marc Jones, Anjaneya "Reddy" Chagam, Stefan Reinauer, Christian Walter, David Hendricks, Angel Pons, Subrata Banik, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52735 to look at the new patch set (#2). Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change ...................................................................... doc/relnotes/4.14: add Intel Xeon-SP support status change Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e --- M Documentation/releases/coreboot-4.14-relnotes.md 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52735/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Gerrit-Change-Number: 52735 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED
by Furquan Shaikh (Code Review) 03 May '21

03 May '21

Attention is currently required from: Martin Roth. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52763 ) Change subject: soc/amd/common: Add placeholder GPIO macro, PAD_UNCHANGED ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52763/comment/6c63d68a_21a3f2c3 PS1, Line 9: GPIOs can only be updated in gpio_configure_pads_with_override() if they : are present in the base table. If they are not there, the override : does not work. This allows them to be in the base table so that they can : be overridden without changing the existing configuration. > Why must a mainboard configure all pads in ramstage? ramstage is the place in coreboot where all the platform initialization happens in order to prepare the platform for payload or OS usage. All the stages prior to that are primarily to be able to boot to ramstage by doing whatever is essential - verified boot, DRAM init, etc. For these cases, yes, certain GPIOs might have to be configured. But, ramstage is the point where we are preparing the platform to jump to OS/payload and hence all subsystems are initialized,resources are allocated, etc. Hence, my comment that all pads must be initialized in ramstage. I understand that we have also been using early stages to drive GPIOs certain way to meet power sequencing requirements and hence some GPIOs might be configured early on before ramstage. My point about always configuring the pads in ramstage is to avoid the same issue that you mentioned about adding in one place and forgetting ramstage. If all pads are always added to ramstage, we do not need to worry about whether the pad is configured in early stage or not, or if it is missed in ramstage whether that was an intentional or just a missed configuration. I think it keeps things simpler for the author as well as the reviewer. > If that's a bad plan, and we really want to update every gpio pad in ramstage, whether they've already been set or not I can do that, but I honestly believe that it will lead to bugs down the line. What kind of bugs are you worried about? I don't think it is a bad plan, but would like to understand what bugs you are thinking about. -- To view, visit https://review.coreboot.org/c/coreboot/+/52763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e5e7b7d30f2c89fa1db375ddba394e6914d97b9 Gerrit-Change-Number: 52763 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 03 May 2021 21:14:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: doc/relnotes/4.14: add Intel Xeon-SP support status change
by Jonathan Zhang (Code Review) 03 May '21

03 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Christian Walter, Stefan Reinauer, David Hendricks, Angel Pons, Subrata Banik, Ron Minnich. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52735 ) Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change ...................................................................... Patch Set 1: (3 comments) File Documentation/releases/coreboot-4.14-relnotes.md: https://review.coreboot.org/c/coreboot/+/52735/comment/9eecd75c_807f236c PS1, Line 55: Sacalable > Scalable Ack https://review.coreboot.org/c/coreboot/+/52735/comment/9276f25f_4568e6c1 PS1, Line 55: became > nit: I'd say `is now considered` Ack https://review.coreboot.org/c/coreboot/+/52735/comment/bbb3521f_bdede9cc PS1, Line 58: of > of the? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Gerrit-Change-Number: 52735 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 03 May 2021 21:14:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Clean up FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52846 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/alderlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 5 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/52846/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Gerrit-Change-Number: 52846 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52845 to look at the new patch set (#7). Change subject: soc/intel/jasperlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/jasperlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 5 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/52845/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I367554053f78b760ece6d59f79ce1f0e0f9fdfc6 Gerrit-Change-Number: 52845 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52844 to look at the new patch set (#7). Change subject: soc/intel/tigerlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/tigerlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 5 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/52844/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0580fb3ec9daafac273dcb091f48ce403c22e8f8 Gerrit-Change-Number: 52844 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Clean up FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52843 to look at the new patch set (#6). Change subject: soc/intel/skylake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/skylake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-clause and adjust comments. This changes behavior since now related options are always set, depending on if coreboot or the FSP should be responsible for the chipset lockdown. This ensures a defined state independent from the default configuration of the FSP. Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/chip.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/52843/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c43a11a40a474de4af22aa5506b1d387809bda2 Gerrit-Change-Number: 52843 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52842 to look at the new patch set (#5). Change subject: soc/intel/cannonlake: Clean up FSP chipset lockdown configuration ...................................................................... soc/intel/cannonlake: Clean up FSP chipset lockdown configuration Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause and adjust comments. Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 12 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52842/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I202c212ec8e9ac63f5512c2e74040c23e1562b9a Gerrit-Change-Number: 52842 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Tim Wawrzynczak (Code Review) 03 May '21

03 May '21

Attention is currently required from: Star Labs, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 ) Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: just curious, have you seen CB:37115 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 4 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 May 2021 21:13:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021