coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/mancomb: Switch eSPI ALERT# to in-band
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52956 ) Change subject: mb/google/mancomb: Switch eSPI ALERT# to in-band ...................................................................... mb/google/mancomb: Switch eSPI ALERT# to in-band This matches what we are doing on guybrush. BUG=b:187122344, b:186135022 TEST=build Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id61de28cd0ee762693b287b29bdd7605d4176929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52956 Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 88c09ac..7ed9c1b 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -31,7 +31,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .alert_pin = ESPI_ALERT_PIN_IN_BAND, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/52956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id61de28cd0ee762693b287b29bdd7605d4176929 Gerrit-Change-Number: 52956 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Diana Zigterman <dzigterman(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Switch eSPI ALERT# to in-band
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52955 ) Change subject: mb/google/guybrush: Switch eSPI ALERT# to in-band ...................................................................... mb/google/guybrush: Switch eSPI ALERT# to in-band Using the push-pull alert was causing leakages when in S0i3. This is because the EC drives ALERT#, so when the AP enters S0i3, the extra current leaks into the SoC and ends up turning on the power regulators. By using in-band ALERT#, the EC no longer drives this pin high, thus fixing the leak. We could also have used an open drain alert, but the rise time is less than ideal. BUG=b:187122344, b:186135022 TEST=Measure S0i3 power on guybrush and validate it's no longer high. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 061b275..88a0a1c 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -35,7 +35,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .alert_pin = ESPI_ALERT_PIN_IN_BAND, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/52955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562 Gerrit-Change-Number: 52955 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/espi,mb/: Allow configuring open drain ALERT#
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52954 ) Change subject: soc/amd/common/espi,mb/: Allow configuring open drain ALERT# ...................................................................... soc/amd/common/espi,mb/: Allow configuring open drain ALERT# Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/majolica/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/soc/amd/common/block/include/amdblocks/espi.h M src/soc/amd/common/block/lpc/espi_util.c 10 files changed, 39 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 5429234..a3385b9 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -120,7 +120,7 @@ .io_mode = ESPI_IO_MODE_SINGLE, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 0, .vw_ch_en = 0, .oob_ch_en = 0, diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index 502ae25..422c009 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -7,7 +7,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 1, diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index c02cb8a..ee0af53 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -120,7 +120,7 @@ .io_mode = ESPI_IO_MODE_SINGLE, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 0, .vw_ch_en = 0, .oob_ch_en = 0, diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 1a86ab7..994c910 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -120,7 +120,7 @@ .io_mode = ESPI_IO_MODE_SINGLE, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 0, .vw_ch_en = 0, .oob_ch_en = 0, diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 3097425..061b275 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -35,7 +35,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index ab5ade7..88c09ac 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -31,7 +31,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index f0fcf37..a8c270e 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -230,7 +230,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index ececa3e..840dfe7 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -223,7 +223,7 @@ .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, .crc_check_enable = 1, - .dedicated_alert_pin = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, .periph_ch_en = 1, .vw_ch_en = 1, .oob_ch_en = 0, diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index 82bfcbe..5d75835 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -73,6 +73,12 @@ ESPI_OP_FREQ_66_MHZ = ESPI_OP_FREQ_VALUE(2), }; +enum espi_alert_pin { + ESPI_ALERT_PIN_IN_BAND, + ESPI_ALERT_PIN_PUSH_PULL, + ESPI_ALERT_PIN_OPEN_DRAIN, +}; + struct espi_config { /* Bitmap for standard IO decodes. Use ESPI_DECODE_IO_* above. */ uint32_t std_io_decode_bitmap; @@ -85,9 +91,9 @@ /* Slave configuration parameters */ enum espi_io_mode io_mode; enum espi_op_freq op_freq_mhz; + enum espi_alert_pin alert_pin; uint32_t crc_check_enable:1; - uint32_t dedicated_alert_pin:1; uint32_t periph_ch_en:1; uint32_t vw_ch_en:1; uint32_t oob_ch_en:1; diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 519130a6..81056b0 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -683,6 +683,29 @@ } } +static void espi_set_alert_pin_config(enum espi_alert_pin alert_pin, uint32_t slave_caps, + uint32_t *slave_config, uint32_t *ctrlr_config) +{ + switch (alert_pin) { + case ESPI_ALERT_PIN_IN_BAND: + *slave_config |= ESPI_SLAVE_ALERT_MODE_IO1; + return; + case ESPI_ALERT_PIN_PUSH_PULL: + *slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_PUSH_PULL_ALERT_SEL; + *ctrlr_config |= ESPI_ALERT_MODE; + return; + case ESPI_ALERT_PIN_OPEN_DRAIN: + if (!(slave_caps & ESPI_SLAVE_OPEN_DRAIN_ALERT_SUPP)) + die("eSPI peripheral does not support open drain alert!"); + + *slave_config |= ESPI_SLAVE_ALERT_MODE_PIN | ESPI_SLAVE_OPEN_DRAIN_ALERT_SEL; + *ctrlr_config |= ESPI_ALERT_MODE; + return; + default: + die("Unknown espi alert config: %u!\n", alert_pin); + } +} + static int espi_set_general_configuration(const struct espi_config *mb_cfg, uint32_t slave_caps) { uint32_t slave_config = 0; @@ -693,11 +716,7 @@ ctrlr_config |= ESPI_CRC_CHECKING_EN; } - if (mb_cfg->dedicated_alert_pin) { - slave_config |= ESPI_SLAVE_ALERT_MODE_PIN; - ctrlr_config |= ESPI_ALERT_MODE; - } - + espi_set_alert_pin_config(mb_cfg->alert_pin, slave_caps, &slave_config, &ctrlr_config); espi_set_io_mode_config(mb_cfg->io_mode, slave_caps, &slave_config, &ctrlr_config); espi_set_op_freq_config(mb_cfg->op_freq_mhz, slave_caps, &slave_config, &ctrlr_config); -- To view, visit https://review.coreboot.org/c/coreboot/+/52954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Gerrit-Change-Number: 52954 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/espi: Don't set alert pin in espi_set_initial_config
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52953 ) Change subject: soc/amd/common/espi: Don't set alert pin in espi_set_initial_config ...................................................................... soc/amd/common/espi: Don't set alert pin in espi_set_initial_config The eSPI spec says that the Alert Mode defaults to in-band on reset. This change ensures the controller is in sync with the eSPI peripheral. The configured alert mode is configured in espi_set_general_configuration. BUG=b:187122344, b:186135022 TEST=Boot guybrush and make sure we don't get any eSPI errors. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ib43e190d08d77ecfcd22ead2bf42e5de2202b555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52953 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index ade1aaa..519130a6 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -864,9 +864,6 @@ { uint32_t espi_initial_mode = ESPI_OP_FREQ_16_MHZ | ESPI_IO_MODE_SINGLE; - if (mb_cfg->dedicated_alert_pin) - espi_initial_mode |= ESPI_ALERT_MODE; - espi_write32(ESPI_SLAVE0_CONFIG, espi_initial_mode); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43e190d08d77ecfcd22ead2bf42e5de2202b555 Gerrit-Change-Number: 52953 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/espi: Print set eSPI peripheral config
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52952 ) Change subject: soc/amd/common/espi: Print set eSPI peripheral config ...................................................................... soc/amd/common/espi: Print set eSPI peripheral config This will print the config we are setting on the eSPI peripheral. e.g., Setting general configuration: slave: 0x98a00000 controller: 0xe2000000 eSPI Slave configuration: CRC checking enabled Dedicated Alert# used to signal alert event eSPI quad IO mode selected Only eSPI single IO mode supported Alert# pin is open-drain eSPI 33MHz selected eSPI up to 20MHz supported Maximum Wait state: 0 BUG=b:187122344, b:186135022 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52952 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Rob Barnes: Looks good to me, but someone else must approve diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 7752eb5..ade1aaa 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -705,6 +705,8 @@ printk(BIOS_INFO, "Setting general configuration: slave: 0x%x controller: 0x%x\n", slave_config, ctrlr_config); + espi_show_slave_general_configuration(slave_config); + if (espi_set_configuration(ESPI_SLAVE_GENERAL_CFG, slave_config) == -1) return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/52952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9 Gerrit-Change-Number: 52952 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/{common/picasso}: Move pci_int.asl
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52916 ) Change subject: soc/amd/{common/picasso}: Move pci_int.asl ...................................................................... soc/amd/{common/picasso}: Move pci_int.asl We can share this with cezanne. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: If746d55345f6b7c828376b64adc5532d20413f68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52916 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- R src/soc/amd/common/acpi/pci_int.asl M src/soc/amd/picasso/acpi/soc.asl 2 files changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/picasso/acpi/pci_int.asl b/src/soc/amd/common/acpi/pci_int.asl similarity index 100% rename from src/soc/amd/picasso/acpi/pci_int.asl rename to src/soc/amd/common/acpi/pci_int.asl diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index b411c20..e8c78e1 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -9,7 +9,7 @@ } /* Describe PCI INT[A-H] for the Southbridge */ -#include "pci_int.asl" +#include <soc/amd/common/acpi/pci_int.asl> /* Describe the devices in the Southbridge */ #include "sb_fch.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/52916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If746d55345f6b7c828376b64adc5532d20413f68 Gerrit-Change-Number: 52916 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Populate PIC IRQ data
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52915 ) Change subject: mb/google/guybrush: Populate PIC IRQ data ...................................................................... Patch Set 3: Code-Review+2 (2 comments) Patchset: PS2: > Yeah we should add them in a followup. I think it will only affect Seabios. ok. maybe create a bug or just keep that in your local list of things to do if you have a local list for that Patchset: PS3: haven't verified if those numbers are good for all sorts of device combinations, but didn't spot anything that looked obviously wrong -- To view, visit https://review.coreboot.org/c/coreboot/+/52915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f Gerrit-Change-Number: 52915 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 06 May 2021 23:26:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: cezanne/psp_verstage: reduce memory usage
by Kangheui Won (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52751 ) Change subject: cezanne/psp_verstage: reduce memory usage ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52751/comment/3c2f3a65_22790a75 PS1, Line 7: usgae > Usage Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30730a6dc53e2449981c635ecfe63029c73e58ee Gerrit-Change-Number: 52751 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 06 May 2021 23:25:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Populate PCI_INTR registers
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52914 ) Change subject: soc/amd/cezanne: Populate PCI_INTR registers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0 Gerrit-Change-Number: 52914 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 06 May 2021 23:24:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/pci: Implement populate_pirq_data
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52913 ) Change subject: soc/amd/common/fsp/pci: Implement populate_pirq_data ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/common/fsp/pci/pirq.c: https://review.coreboot.org/c/coreboot/+/52913/comment/8336a5ed_c16cb149 PS3, Line 19: might be a good idea to check if entries is != 0 before calling calloc https://review.coreboot.org/c/coreboot/+/52913/comment/01650d38_4bd9cfaa PS3, Line 23: return; add some BIOS_ERR printk here? for a valid routing table calloc isn't supposed to return NULL -- To view, visit https://review.coreboot.org/c/coreboot/+/52913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869 Gerrit-Change-Number: 52913 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Thu, 06 May 2021 23:24:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021