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Change in coreboot[master]: soc/mediatek/mt8195: Configure eMMC and SDCard
by Rex-BC Chen (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin, Yidi Lin. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/53895 to review the following change. Change subject: soc/mediatek/mt8195: Configure eMMC and SDCard ...................................................................... soc/mediatek/mt8195: Configure eMMC and SDCard Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/mt8195/Makefile.inc 3 files changed, 120 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/53895/1 diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index a1aa2fd..4720dc5 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -12,4 +12,5 @@ ramstage-y += memlayout.ld ramstage-y += chromeos.c +ramstage-y += mainboard.c ramstage-y += reset.c diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c new file mode 100644 index 0000000..73f1d4e --- /dev/null +++ b/src/mainboard/google/cherry/mainboard.c @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/mmio.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/i2c.h> +#include <soc/mt6360.h> +#include <soc/regulator.h> + +DEFINE_BITFIELD(MSDC0_DRV, 29, 0) +DEFINE_BITFIELD(MSDC1_DRV, 17, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_0, 26, 24) +DEFINE_BITFIELD(MSDC1_GPIO_MODE0_1, 30, 28) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_0, 2, 0) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_1, 6, 4) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_2, 10, 8) +DEFINE_BITFIELD(MSDC1_GPIO_MODE1_3, 14, 12) + +#define MSDC0_DRV_VALUE 0x1b6db6db +#define MSDC1_DRV_VALUE 0x1b6db +#define MSDC1_GPIO_MODE0_VALUE 0x1 +#define MSDC1_GPIO_MODE1_VALUE 0x1 + +enum { + MSDC1_GPIO_MODE0_BASE = 0x100053d0, + MSDC1_GPIO_MODE1_BASE = 0x100053e0, +}; + +static void configure_emmc(void) +{ + void *gpio_base = (void *)IOCFG_TL_BASE; + int i; + + const gpio_t emmc_pu_pin[] = { + GPIO(EMMC_DAT0), GPIO(EMMC_DAT1), + GPIO(EMMC_DAT2), GPIO(EMMC_DAT3), + GPIO(EMMC_DAT4), GPIO(EMMC_DAT5), + GPIO(EMMC_DAT6), GPIO(EMMC_DAT7), + GPIO(EMMC_CMD), GPIO(EMMC_RSTB), + }; + + const gpio_t emmc_pd_pin[] = { + GPIO(EMMC_DSL), GPIO(EMMC_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(emmc_pu_pin); i++) + gpio_set_pull(emmc_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(emmc_pd_pin); i++) + gpio_set_pull(emmc_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set eMMC cmd/dat/clk/ds/rstb pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC0_DRV, MSDC0_DRV_VALUE); +} + +static void configure_sdcard(void) +{ + void *gpio_base = (void *)IOCFG_RB_BASE; + void *gpio_mode0_base = (void *)MSDC1_GPIO_MODE0_BASE; + void *gpio_mode1_base = (void *)MSDC1_GPIO_MODE1_BASE; + int i; + + const gpio_t sdcard_pu_pin[] = { + GPIO(MSDC1_DAT0), GPIO(MSDC1_DAT1), + GPIO(MSDC1_DAT2), GPIO(MSDC1_DAT3), + GPIO(MSDC1_CMD), + }; + + const gpio_t sdcard_pd_pin[] = { + GPIO(MSDC1_CLK), + }; + + for (i = 0; i < ARRAY_SIZE(sdcard_pu_pin); i++) + gpio_set_pull(sdcard_pu_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_UP); + + for (i = 0; i < ARRAY_SIZE(sdcard_pd_pin); i++) + gpio_set_pull(sdcard_pd_pin[i], GPIO_PULL_ENABLE, GPIO_PULL_DOWN); + + /* set sdcard cmd/dat/clk pins driving to 8mA */ + SET32_BITFIELDS(gpio_base, MSDC1_DRV, MSDC1_DRV_VALUE); + + /* set sdcard dat2/dat0/dat3/cmd/clk pins to msdc1 mode */ + SET32_BITFIELDS(gpio_mode0_base, + MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, + MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE); + + /* set sdcard dat1 pin to msdc1 mode */ + SET32_BITFIELDS(gpio_mode1_base, + MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE, + MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE); + + mtk_i2c_bus_init(7); + mt6360_init(7); + mt6360_ldo_enable(MT6360_LDO3, 1); + mt6360_ldo_enable(MT6360_LDO5, 1); +} + +static void mainboard_init(struct device *dev) +{ + configure_emmc(); + configure_sdcard(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index aca3905..c344849 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += ../common/timer.c timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/wdt.c +ramstage-y += mt6360.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8195/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/53895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Gerrit-Change-Number: 53895 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Add i2c driver support
by Rex-BC Chen (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53894 ) Change subject: soc/mediatek/mt8195: Add i2c driver support ...................................................................... soc/mediatek/mt8195: Add i2c driver support TEST=write/read EEPROM on MT8195 EVB successfully Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Signed-off-by: kewei xu <kewei.xu(a)mediatek.com> --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/i2c.c A src/soc/mediatek/mt8195/include/soc/i2c.h 3 files changed, 229 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/53894/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index f848f7b..aca3905 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/flash_controller.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -12,6 +13,7 @@ verstage-y += ../common/flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c timer.c verstage-y += ../common/uart.c @@ -21,6 +23,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c timer.c @@ -35,6 +38,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8195/i2c.c b/src/soc/mediatek/mt8195/i2c.c new file mode 100644 index 0000000..6a959b2 --- /dev/null +++ b/src/soc/mediatek/mt8195/i2c.c @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +#define I2C_FULL_DUTY 100 +#define I2C_HALF_DUTY 50 +#define I2C_ADJUSTED_DUTY 50 +#define I2C_FS_START_CON 0x0 +struct mtk_i2c mtk_i2c_bus_controller[] = { + [0] = { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [1] = { + .i2c_regs = (void *)(I2C_BASE + 0x1000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x180), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [2] = { + .i2c_regs = (void *)(I2C_BASE + 0x2000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x300), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [3] = { + .i2c_regs = (void *)(I2C_BASE + 0x3000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [4] = { + .i2c_regs = (void *)(I2C_BASE + 0x4000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [5] = { + .i2c_regs = (void *)(I2C_BASE - 0x100000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x500), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [6] = { + .i2c_regs = (void *)(I2C_BASE - 0xFF000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + [7] = { + .i2c_regs = (void *)(I2C_BASE - 0xFE000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x600), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + [0] = { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + [1] = { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + [2] = { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + [3] = { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + [4] = { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + [5] = { + PAD_FUNC(HDMIRX_SCL, SCL5), + PAD_FUNC(HDMIRX_SDA, SDA5), + }, + [6] = { + PAD_FUNC(HDMITX_SCL, SCL6), + PAD_FUNC(HDMITX_SDA, SDA6), + }, + [7] = { + PAD_FUNC(HDMIRX_HTPLG, SCL7), + PAD_FUNC(HDMIRX_PWR5V, SDA7), + }, + +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + if (bus <= I2C4) + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + uint32_t tar_speed = 400; + uint32_t tar_speed_high; + uint32_t tar_speed_low; + + assert(bus < I2C_BUS_NUMBER); + + /* Adjust ratio of high/low level */ + tar_speed_high = tar_speed * I2C_HALF_DUTY / I2C_ADJUSTED_DUTY; + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (tar_speed_high * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && + i2c_freq <= tar_speed_high * KHz && + i2c_freq >= (tar_speed_high - 20) * KHz); + + /* Init i2c bus timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + + /* Adjust ratio of high/low level */ + tar_speed_low = tar_speed * I2C_HALF_DUTY / + (I2C_FULL_DUTY - I2C_ADJUSTED_DUTY); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (tar_speed_low * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && + i2c_freq <= tar_speed_low * KHz && + i2c_freq >= (tar_speed_low - 20) * KHz); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, + clock_div - 1); + + /* Adjust tSU,STA/tHD,STA/tSU,STO */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ext_conf, I2C_FS_START_CON); +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8195/include/soc/i2c.h b/src/soc/mediatek/mt8195/include/soc/i2c.h new file mode 100644 index 0000000..977106e --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/i2c.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_I2C_H +#define SOC_MEDIATEK_MT8195_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +/* I2C ID Number*/ +enum { + I2C0, + I2C1, + I2C2, + I2C3, + I2C4, + I2C5, + I2C6, + I2C7, +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8195_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Gerrit-Change-Number: 53894 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Add mt6360 driver for LDO access
by Rex-BC Chen (Code Review) 07 May '21

07 May '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53893 ) Change subject: soc/mediatek/mt8195: Add mt6360 driver for LDO access ...................................................................... soc/mediatek/mt8195: Add mt6360 driver for LDO access Signed-off-by: Andrew SH Cheng <andrew-sh.cheng(a)mediatek.com> Change-Id: I68ca7067f76a67c4e797437593539f8f85909edc --- A src/soc/mediatek/mt8195/include/soc/mt6360.h A src/soc/mediatek/mt8195/mt6360.c 2 files changed, 357 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/53893/1 diff --git a/src/soc/mediatek/mt8195/include/soc/mt6360.h b/src/soc/mediatek/mt8195/include/soc/mt6360.h new file mode 100644 index 0000000..3ac66fa --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/mt6360.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8195_MT6360_H__ +#define __SOC_MEDIATEK_MT8195_MT6360_H__ + +#include <stdint.h> + +enum mt6360_ldo_id { + MT6360_LDO1 = 0, + MT6360_LDO2, + MT6360_LDO3, + MT6360_LDO5, + MT6360_LDO_COUNT, +}; + +#define MT6360_LDO_I2C_ADDR 0x64 +#define MT6360_PMIC_I2C_ADDR 0x1A + +void mt6360_init(uint8_t bus); +void mt6360_ldo_enable(enum mt6360_ldo_id ldo_id, uint8_t enable); +uint8_t mt6360_ldo_is_enabled(enum mt6360_ldo_id ldo_id); +void mt6360_ldo_set_voltage(enum mt6360_ldo_id ldo_id, u32 voltage_uv); +u32 mt6360_ldo_get_voltage(enum mt6360_ldo_id ldo_id); +#endif diff --git a/src/soc/mediatek/mt8195/mt6360.c b/src/soc/mediatek/mt8195/mt6360.c new file mode 100644 index 0000000..4b07cf1 --- /dev/null +++ b/src/soc/mediatek/mt8195/mt6360.c @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/i2c_simple.h> +#include <soc/mt6360.h> +#include <stdbool.h> +#include <string.h> + +enum { + LDO_INDEX = 0, + PMIC_INDEX, +}; + +struct mt6360_i2c_data { + u8 bus; + u8 addr; +}; + +static struct mt6360_i2c_data i2c_data[] = { + [LDO_INDEX] = { + .addr = MT6360_LDO_I2C_ADDR, + }, + [PMIC_INDEX] = { + .addr = MT6360_PMIC_I2C_ADDR, + }, +}; + +static const uint32_t mt6360_ldo1_vsel_table[0x10] = { + [0x4] = 1800000, + [0x5] = 2000000, + [0x6] = 2100000, + [0x7] = 2500000, + [0x8] = 2700000, + [0x9] = 2800000, + [0xA] = 2900000, + [0xB] = 3000000, + [0xC] = 3100000, + [0xD] = 3300000, +}; + +static const uint32_t mt6360_ldo3_vsel_table[0x10] = { + [0x4] = 1800000, + [0xA] = 2900000, + [0xB] = 3000000, + [0xD] = 3300000, +}; + +static const uint32_t mt6360_ldo5_vsel_table[0x10] = { + [0x2] = 2900000, + [0x3] = 3000000, + [0x5] = 3300000, +}; + +struct mt6360_ldo_data { + uint8_t enable_reg; + uint8_t enable_mask; + uint8_t vsel_reg; + uint8_t vsel_mask; + const uint32_t *vsel_table; + uint32_t vsel_table_len; +}; + +#define MT6360_LDO_DATA(_enreg, _enmask, _vreg, _vmask, _table) \ +{ \ + .enable_reg = _enreg, \ + .enable_mask = _enmask, \ + .vsel_reg = _vreg, \ + .vsel_mask = _vmask, \ + .vsel_table = _table, \ + .vsel_table_len = ARRAY_SIZE(_table), \ +} + + +static const struct mt6360_ldo_data ldo_data[MT6360_LDO_COUNT] = { + [MT6360_LDO1] = MT6360_LDO_DATA(0x17, 0x40, 0x1B, 0xFF, mt6360_ldo1_vsel_table), + [MT6360_LDO2] = MT6360_LDO_DATA(0x11, 0x40, 0x15, 0xFF, mt6360_ldo1_vsel_table), + [MT6360_LDO3] = MT6360_LDO_DATA(0x05, 0x40, 0x09, 0xFF, mt6360_ldo3_vsel_table), + [MT6360_LDO5] = MT6360_LDO_DATA(0x0B, 0x40, 0x0F, 0xFF, mt6360_ldo5_vsel_table), +}; + +#define CRC8_TABLE_SIZE 256 +static u8 crc8_table[CRC8_TABLE_SIZE]; + +static u8 crc8(const u8 table[CRC8_TABLE_SIZE], u8 *pdata, size_t nbytes) +{ + u8 crc = 0; + + while (nbytes-- > 0) + crc = table[(crc ^ *pdata++) & 0xff]; + + return crc; +} + +static int mt6360_i2c_write_byte(struct mt6360_i2c_data *i2c, u8 reg, u8 data) +{ + u8 chunk[5] = { 0 }; + + if ((reg & 0xc0) != 0) { + printk(BIOS_ERR, "%s: not support reg [%#x]\n", __func__, reg); + return -1; + } + + /* + * chunk[0], dev address + * chunk[1], reg address + * chunk[2], data to write + * chunk[3], crc of chunk[0 ~ 2] + * chunk[4], blank + */ + chunk[0] = (i2c->addr & 0x7f) << 1; + chunk[1] = (reg & 0x3f); + chunk[2] = data; + chunk[3] = crc8(crc8_table, chunk, 3); + + return i2c_write_raw(i2c->bus, i2c->addr, &chunk[1], 4); +} + +static int mt6360_i2c_read_byte(struct mt6360_i2c_data *i2c, u8 reg, u8 *data) +{ + u8 chunk[4] = { 0 }; + u8 buf[2]; + int ret; + u8 crc; + + ret = i2c_read_bytes(i2c->bus, i2c->addr, reg & 0x3f, buf, 2); + + if (ret) + return ret; + /* + * chunk[0], dev address + * chunk[1], reg address + * chunk[2], received data + * chunk[3], received crc of chunk[0 ~ 2] + */ + chunk[0] = ((i2c->addr & 0x7f) << 1) + 1; + chunk[1] = (reg & 0x3f); + chunk[2] = buf[0]; + chunk[3] = buf[1]; + crc = crc8(crc8_table, chunk, 3); + + if (chunk[3] != crc) { + printk(BIOS_ERR, "%s: incorrect CRC: expected %#x, got %#x", + __func__, crc, chunk[3]); + return -1; + } + + *data = chunk[2]; + + return 0; +} + +static int mt6360_read_interface(u8 index, u8 reg, u8 *data, u8 mask, u8 shift) +{ + int ret; + u8 val = 0; + + ret = mt6360_i2c_read_byte(&i2c_data[index], reg, &val); + if (ret < 0) { + printk(BIOS_ERR, "%s: fail, reg = %#x, ret = %d\n", + __func__, reg, ret); + return ret; + } + val &= (mask << shift); + *data = (val >> shift); + return 0; +} + +static int mt6360_config_interface(u8 index, u8 reg, u8 data, u8 mask, u8 shift) +{ + int ret; + u8 val = 0; + + ret = mt6360_i2c_read_byte(&i2c_data[index], reg, &val); + if (ret < 0) { + printk(BIOS_ERR, "%s: fail, reg = %#x, ret = %d\n", + __func__, reg, ret); + return ret; + } + val &= ~(mask << shift); + val |= (data << shift); + + return mt6360_i2c_write_byte(&i2c_data[index], reg, val); +} + +static bool is_valid_ldo(enum mt6360_ldo_id id) +{ + if (id >= MT6360_LDO_COUNT) { + printk(BIOS_ERR, "%s: LDO %d is not supported\n", __func__, id); + return false; + } + + return true; +} + +void mt6360_ldo_enable(enum mt6360_ldo_id id, uint8_t enable) +{ + u8 val; + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return; + + data = &ldo_data[id]; + + if (mt6360_read_interface(LDO_INDEX, data->enable_reg, &val, 0xFF, 0) < 0) + return; + + if (enable) + val |= data->enable_mask; + else + val &= ~(data->enable_mask); + + mt6360_config_interface(LDO_INDEX, data->enable_reg, val, 0xFF, 0); +} + +uint8_t mt6360_ldo_is_enabled(enum mt6360_ldo_id id) +{ + u8 val; + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return 0; + + data = &ldo_data[id]; + + if (mt6360_read_interface(LDO_INDEX, data->enable_reg, &val, 0xFF, 0) < 0) + return 0; + + return (val & data->enable_mask) ? 1 : 0; +} + +void mt6360_ldo_set_voltage(enum mt6360_ldo_id id, u32 voltage_uv) +{ + u8 val = 0; + u32 voltage_uv_temp = 0; + int i; + + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return; + + data = &ldo_data[id]; + + for (i = 0; i < data->vsel_table_len; i++) { + u32 uv = data->vsel_table[i]; + + if (uv == 0) + continue; + if (uv > voltage_uv) + break; + + val = i << 4; + voltage_uv_temp = voltage_uv - uv; + } + + if (val == 0) { + printk(BIOS_ERR, "%s: LDO %d, set %d uV not supported\n", + __func__, id, voltage_uv); + return; + } + + voltage_uv_temp /= 10000; + voltage_uv_temp = MIN(voltage_uv_temp, 0xA); + val |= (u8)voltage_uv_temp; + + mt6360_config_interface(LDO_INDEX, data->vsel_reg, val, 0xFF, 0); +} + +u32 mt6360_ldo_get_voltage(enum mt6360_ldo_id id) +{ + u8 val; + u32 voltage_uv; + + const struct mt6360_ldo_data *data; + + if (!is_valid_ldo(id)) + return 0; + + data = &ldo_data[id]; + + if (mt6360_read_interface(LDO_INDEX, data->vsel_reg, &val, 0xFF, 0) < 0) + return 0; + + voltage_uv = data->vsel_table[(val & 0xF0) >> 4]; + if (voltage_uv == 0) { + printk(BIOS_ERR, "%s: LDO %d read fail, reg = %#x\n", __func__, id, val); + return 0; + } + + val = MIN(val & 0x0F, 0x0A); + voltage_uv += val * 10000; + + return voltage_uv; +} + +static void crc8_populate_msb(u8 table[CRC8_TABLE_SIZE], u8 polynomial) +{ + int i, j; + const u8 msbit = 0x80; + u8 t = msbit; + + table[0] = 0; + + for (i = 1; i < CRC8_TABLE_SIZE; i *= 2) { + t = (t << 1) ^ (t & msbit ? polynomial : 0); + for (j = 0; j < i; j++) + table[i + j] = table[j] ^ t; + } +} + +void mt6360_init(uint8_t bus) +{ + u8 delay01, delay02, delay03, delay04; + + crc8_populate_msb(crc8_table, 0x7); + + i2c_data[LDO_INDEX].bus = bus; + i2c_data[PMIC_INDEX].bus = bus; + + mt6360_config_interface(PMIC_INDEX, 0x07, 0x04, 0xFF, 0); + mt6360_config_interface(PMIC_INDEX, 0x08, 0x00, 0xFF, 0); + mt6360_config_interface(PMIC_INDEX, 0x09, 0x02, 0xFF, 0); + mt6360_config_interface(PMIC_INDEX, 0x0A, 0x00, 0xFF, 0); + + mt6360_read_interface(PMIC_INDEX, 0x07, &delay01, 0xFF, 0); + mt6360_read_interface(PMIC_INDEX, 0x08, &delay02, 0xFF, 0); + mt6360_read_interface(PMIC_INDEX, 0x09, &delay03, 0xFF, 0); + mt6360_read_interface(PMIC_INDEX, 0x0A, &delay04, 0xFF, 0); + printk(BIOS_DEBUG, + "%s: power off sequence delay: %#x, %#x, %#x, %#x\n", + __func__, delay01, delay02, delay03, delay04); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/53893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68ca7067f76a67c4e797437593539f8f85909edc Gerrit-Change-Number: 53893 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Patrick Rudolph (Code Review) 07 May '21

07 May '21

Attention is currently required from: Star Labs. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... Patch Set 6: (4 comments) File .tmpconfig.lintn90hoF: PS6: seems accidentally added File src/ec/starlabs/it8987/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/52797/comment/8cd8cec5_8f27f15f PS6, Line 79: Not remove dead code File src/ec/starlabs/it8987/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/52797/comment/995f4002_e5a95c6b PS6, Line 169: SMB2 unused code File src/ec/starlabs/it8987/ec.h: https://review.coreboot.org/c/coreboot/+/52797/comment/768ac769_44c7b4ae PS6, Line 11: 0x4e shouldn't that be provided by mainboard code as it could be 0x2e as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 6 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Comment-Date: Fri, 07 May 2021 05:53:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/intel: Add LOCKDIS to mark SPI as writable in SKL
by Patrick Rudolph (Code Review) 07 May '21

07 May '21

Attention is currently required from: Star Labs. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52796 ) Change subject: src/intel: Add LOCKDIS to mark SPI as writable in SKL ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Please go more I to detail here. By default coreboot does not write protect anything in the SPI flash and there's no SMM handler to protect the flash. If fwupd can't detect that it might needs to be fixed, not coreboot. Not locking anything might be useful for debugging, but it should not made it into a devicetree setting used by default. -- To view, visit https://review.coreboot.org/c/coreboot/+/52796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I712972428dd22373d8655ce72d36c0957ee9a900 Gerrit-Change-Number: 52796 Gerrit-PatchSet: 4 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-Comment-Date: Fri, 07 May 2021 05:24:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Update pirika device tree
by Kirk Wang (Code Review) 07 May '21

07 May '21

Attention is currently required from: Paul2 Huang, Alex1 Kao. Kirk Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52936 ) Change subject: mb/google/dedede: Update pirika device tree ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15b9cb0d0276b5e2dd06694530cc35e5643efb9d Gerrit-Change-Number: 52936 Gerrit-PatchSet: 2 Gerrit-Owner: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 May 2021 03:50:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add GPIO and SPD for pirika support
by Alex1 Kao (Code Review) 07 May '21

07 May '21

Attention is currently required from: Paul2 Huang, Kirk Wang. Alex1 Kao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52923 ) Change subject: mb/google/dedede: Add GPIO and SPD for pirika support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c Gerrit-Change-Number: 52923 Gerrit-PatchSet: 1 Gerrit-Owner: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 May 2021 03:50:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Add GPIO and SPD for pirika support
by Kirk Wang (Code Review) 07 May '21

07 May '21

Attention is currently required from: Paul2 Huang, Alex1 Kao. Kirk Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52923 ) Change subject: mb/google/dedede: Add GPIO and SPD for pirika support ...................................................................... Patch Set 1: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/52923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c Gerrit-Change-Number: 52923 Gerrit-PatchSet: 1 Gerrit-Owner: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 May 2021 03:49:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool:cezanne: use correct bootloader binary for whitelist support
by Nikolai Vyssotski (Code Review) 07 May '21

07 May '21

Nikolai Vyssotski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53892 ) Change subject: amdfwtool:cezanne: use correct bootloader binary for whitelist support ...................................................................... amdfwtool:cezanne: use correct bootloader binary for whitelist support PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type 0x73 entry and not type 0x01 (stage1 bootloader). We will also need to change WHL BL filename (Type0x01->Type0x73) in a separate CL. BUG=b:181135622 Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M util/amdfwtool/data_parse.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/53892/1 diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 0c2e71d..e17c2df 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -55,18 +55,14 @@ if (strcmp(fw_name, "PSPBTLDR_WL_FILE") == 0) { if (cb_config->have_whitelist == 1) { - fw_type = AMD_FW_PSP_BOOTLOADER; + fw_type = AMD_FW_PSP_BOOTLOADER_AB; subprog = 0; } else { fw_type = AMD_FW_SKIP; } } else if (strcmp(fw_name, "PSPBTLDR_FILE") == 0) { - if (cb_config->have_whitelist == 0) { - fw_type = AMD_FW_PSP_BOOTLOADER; - subprog = 0; - } else { - fw_type = AMD_FW_SKIP; - } + fw_type = AMD_FW_PSP_BOOTLOADER; + subprog = 0; } else if (strcmp(fw_name, "AMD_PUBKEY_FILE") == 0) { fw_type = AMD_FW_PSP_PUBKEY; subprog = 0; @@ -245,8 +241,12 @@ fw_type = AMD_RPMC_NVRAM; subprog = 0; } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { - fw_type = AMD_FW_PSP_BOOTLOADER_AB; - subprog = 0; + if (cb_config->have_whitelist == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER_AB; + subprog = 0; + } else { + fw_type = AMD_FW_SKIP; + } } else { fw_type = AMD_FW_INVALID; /* TODO: Add more */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Gerrit-Change-Number: 53892 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/mancomb: Fix TPM setting in devicetree
by Ivy Jian (Code Review) 07 May '21

07 May '21

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53891 ) Change subject: mb/google/mancomb: Fix TPM setting in devicetree ...................................................................... mb/google/mancomb: Fix TPM setting in devicetree Fix I2C3 setting for TPM in devicetree. BUG=b:187341277 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 --- M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/53891/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 7ed9c1b..f47074a 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -131,6 +131,15 @@ end end # domain + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + device ref uart_0 on end # UART0 end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/53891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 Gerrit-Change-Number: 53891 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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