coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOO...
by Matt DeVillier (Code Review) 07 May '21

07 May '21

Attention is currently required from: Felix Friedlander, Nico Huber, Martin Roth, Paul Menzel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49233 ) Change subject: payloads/external/tianocore/Kconfig: elaborate help for TIANOCORE_BOOTSPLASH_FILE ...................................................................... Patch Set 1: (1 comment) File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/49233/comment/41778a8d_5b197c82 PS1, Line 100: and will be displayed slightly above the centre of : the screen, > That's also what I recall. However confusing reality might seem, the new […] I'd prefer if this help text were more precise than just "substantially smaller": the boot splash image should be no wider than the pixel width of the panel/resolution set, and no taller than 76.4% of the pixel height of the panel/resolution set (100-(50-38.2)*2). -- To view, visit https://review.coreboot.org/c/coreboot/+/49233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c6666bb0e49369fe8fe2ae3dc12c023f668da0 Gerrit-Change-Number: 49233 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Friedlander <felix(a)ffetc.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Friedlander <felix(a)ffetc.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 07 May 2021 03:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Friedlander <felix(a)ffetc.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/mancomb: Update AMDFW config file
by Martin Roth (Code Review) 07 May '21

07 May '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52900 ) Change subject: mb/google/mancomb: Update AMDFW config file ...................................................................... mb/google/mancomb: Update AMDFW config file Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for the LPDDR4 version. This changes to use SODIMMS. Further changes may be needed for platform customization, so I put the config file in variants/baseboard instead of the root mancomb directory. BUG=b:187094481 TEST=Build only Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/mancomb/Kconfig A src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg 2 files changed, 44 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 552c022..91ec169 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -67,6 +67,10 @@ hex default 0x50 +config AMDFW_CONFIG_FILE + string + default "src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg" + config EFS_SPI_READ_MODE int default 0 if EM100 # Normal read mode diff --git a/src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg b/src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg new file mode 100644 index 0000000..2d4e0f8 --- /dev/null +++ b/src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg @@ -0,0 +1,40 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP + +# type file +# PSP +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn +PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin +PSPBTLDR_WL_FILE TypeId0x01_PspBootLoader_WL_CZN.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin +PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin +PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn +PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin +PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin +PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin +PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin +PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin +PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN.csbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin +DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin +DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin +DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin + +# BDT +PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Ddr4_Udimm_Dmem.csbin +PSP_MP2CFG_FILE MP2FWConfig.sbin -- To view, visit https://review.coreboot.org/c/coreboot/+/52900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Gerrit-Change-Number: 52900 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/mancomb: Update AMDFW config file
by Martin Roth (Code Review) 07 May '21

07 May '21

Attention is currently required from: chris wang. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52900 ) Change subject: mb/google/mancomb: Update AMDFW config file ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/mancomb/variants/baseboard/amdfw.cfg: https://review.coreboot.org/c/coreboot/+/52900/comment/900af606_90d3e25a PS1, Line 37: PSP_PMUI_FILE1 TypeId0x65_Appb_CZN_1D_Ddr4_Udimm_Dmem.csbin : PSP_PMUD_FILE2 TypeId0x64_Appb_CZN_2D_Ddr4_Udimm_Imem.csbin > It should like below. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Gerrit-Change-Number: 52900 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Fri, 07 May 2021 02:54:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: chris wang <Chris.Wang(a)amd.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Yu-Ping Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52925 ) Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/mt8195/mmu_operations.c: PS3: > mtk_soc_after_dram() is different for 8173/8183/8192. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 02:42:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Yu-Ping Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52925 ) Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 02:27:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Yu-Ping Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52924 ) Change subject: mb/google/cherry: configure GPIOs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 02:27:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Xuxin Xiong (Code Review) 07 May '21

07 May '21

Attention is currently required from: Vinod Polimera, Douglas Anderson, Julius Werner. Xuxin Xiong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52959 ) Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: I tested this CL in trogdor firmware branch, and it works well. -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Douglas Anderson <dianders(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 01:56:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer/variant/lindar: Increase Cbfs Mcache size
by Kevin Chang (Code Review) 07 May '21

07 May '21

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53890 ) Change subject: mb/google/volteer/variant/lindar: Increase Cbfs Mcache size ...................................................................... mb/google/volteer/variant/lindar: Increase Cbfs Mcache size Increase Cbfs Mcache size for FAFT fail test item. BUG=b:162052593 TEST=Build FW and boot to OS and test FAFT fail test item. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I84f4f3d7c35165eba9c446ed6658f5bba15c5cfe --- M src/arch/x86/Kconfig M src/lib/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/53890/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index bb03db2..8ad83bc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -145,7 +145,7 @@ Increase this value if preram cbmem console is getting truncated config CBFS_MCACHE_SIZE - hex + hex "CBFS mcache size" depends on !NO_CBFS_MCACHE default 0x2000 help diff --git a/src/lib/Kconfig b/src/lib/Kconfig index e1d56fe..e78629a 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -100,7 +100,7 @@ the respective file. config CBFS_MCACHE_RW_PERCENTAGE - int + int "percentage of the rw mcache" depends on VBOOT && !NO_CBFS_MCACHE default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only default 50 -- To view, visit https://review.coreboot.org/c/coreboot/+/53890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84f4f3d7c35165eba9c446ed6658f5bba15c5cfe Gerrit-Change-Number: 53890 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede: Add a variant callback to update devicetree config
by David Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Karthik Ramasubramanian. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede: Add a variant callback to update devicetree config ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/dedede/variants/metaknight/variant.c: https://review.coreboot.org/c/coreboot/+/52887/comment/29d0a11b_2462cad9 PS2, Line 36: /* Set 1A HDMI configuration */ > Leave USB Port A as a default configuration in the devicetree. […] Thanks. https://review.coreboot.org/c/coreboot/+/52887/comment/48cc041f_6427a8b1 PS2, Line 38: /* Set LTE HDMI configuration */ > Configure the settings as in the devicetree. […] Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 01:09:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/metaknight: Update LTE USB port configuration
by David Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Karthik Ramasubramanian. David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52960 ) Change subject: mb/google/dedede/var/metaknight: Update LTE USB port configuration ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Apply this CL, can fix TypeA device and LTE 5min delay issue. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/52960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Gerrit-Change-Number: 52960 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 01:07:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021