coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: add qclib support
by Ravi kumar (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Martin Roth, mturney mturney, Julius Werner, Sudheer Amrabadi. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, mturney mturney, Julius Werner, Sudheer Amrabadi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50582 to look at the new patch set (#33). Change subject: sc7280: add qclib support ...................................................................... sc7280: add qclib support Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/50582/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/50582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d400f0ad96dbef2e45cc1f11ed17ea95fc60d16 Gerrit-Change-Number: 50582 Gerrit-PatchSet: 33 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cezanne/psp_verstage: reduce memory usage
by Kangheui Won (Code Review) 07 May '21

07 May '21

Kangheui Won has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52751 ) Change subject: cezanne/psp_verstage: reduce memory usage ...................................................................... Abandoned Not needed with new PSP release -- To view, visit https://review.coreboot.org/c/coreboot/+/52751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30730a6dc53e2449981c635ecfe63029c73e58ee Gerrit-Change-Number: 52751 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [RFC] device: Introduce new method for setting device states
by Felix Singer (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Raul Rangel, Furquan Shaikh, Matt DeVillier, Angel Pons, Michael Niewöhner, Patrick Rudolph, Felix Held. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52493 ) Change subject: [RFC] device: Introduce new method for setting device states ...................................................................... Patch Set 20: (1 comment) File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/52493/comment/3c1f3916_baf1e2ca PS13, Line 461: if (!xdci_can_enable()) : params->XdciEnable = 0; > reopened I was about commenting that I don't find this useful since AFAICS there would be only two devices which could make usage of this, and the filter function for one of them just inverts a value which is kind of unnecessary IMO. So there would be only the XDCI device left. For inverting options, we should just use the `invert` attribute. However, I think this could be really useful for hooking up (CMOS) options. AFAIK this is done by each mainboard. So with this, we could easily move some of them to SoC level, maybe even common code. I just would like to rename `filter` to `hook` since there might be more use cases and this one sounds more generic. -- To view, visit https://review.coreboot.org/c/coreboot/+/52493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70fde306c65a8881f565c5f923be20f380ea64d3 Gerrit-Change-Number: 52493 Gerrit-PatchSet: 20 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 06:48:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801ix: Use proper condition for asag locking
by Arthur Heymans (Code Review) 07 May '21

07 May '21

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51524 ) Change subject: sb/intel/i82801ix: Use proper condition for asag locking ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/51524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I729d99f3558fc99c33907eb29ad5dda203763b6e Gerrit-Change-Number: 51524 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting
by Ian Feng (Code Review) 07 May '21

07 May '21

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53901 ) Change subject: mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting ...................................................................... mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting 'hs_bias_sense_en' setting true. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976 --- M src/mainboard/google/octopus/variants/fleex/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/53901/1 diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index f0343cd..f048b54 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -148,6 +148,7 @@ register "bias_lvls[2]" = "4" register "bias_lvls[3]" = "1" register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" + register "hs_bias_sense_en" = "true" device i2c 48 on end end end # - I2C 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/53901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976 Gerrit-Change-Number: 53901 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/intel: Add LOCKDIS to mark SPI as writable in SKL
by Star Labs (Code Review) 07 May '21

07 May '21

Attention is currently required from: Patrick Rudolph. Star Labs has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52796 ) Change subject: src/intel: Add LOCKDIS to mark SPI as writable in SKL ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Please go more I to detail here. […] To clarify, it's just the BIOS Control register - the SPI is indeed writable. coreboot seems to set the BC to 8b for every platform apart from SKL - which is right, locked but writable. On SKL, it sets it to 80, locked and not writable. fwupd was just how I found the issue, but other tools like chipsec also check the same register. -- To view, visit https://review.coreboot.org/c/coreboot/+/52796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I712972428dd22373d8655ce72d36c0957ee9a900 Gerrit-Change-Number: 52796 Gerrit-PatchSet: 4 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 06:33:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Star Labs (Code Review) 07 May '21

07 May '21

Attention is currently required from: Star Labs. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52797 to look at the new patch set (#7). Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... ec: Add Star Labs ITE 8987E support Support for Star Labs labtop series EC Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 --- A src/ec/starlabs/it8987/Kconfig A src/ec/starlabs/it8987/Makefile.inc A src/ec/starlabs/it8987/acpi/ac.asl A src/ec/starlabs/it8987/acpi/battery.asl A src/ec/starlabs/it8987/acpi/cmos.asl A src/ec/starlabs/it8987/acpi/ec.asl A src/ec/starlabs/it8987/acpi/hid.asl A src/ec/starlabs/it8987/acpi/keyboard.asl A src/ec/starlabs/it8987/acpi/lid.asl A src/ec/starlabs/it8987/acpi/thermal.asl A src/ec/starlabs/it8987/chip.h A src/ec/starlabs/it8987/ec.c A src/ec/starlabs/it8987/ec.h 13 files changed, 1,082 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/52797/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 7 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Star Labs <admin(a)starlabs.systems> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mainboard: Add Star Labs labtop series
by Star Labs (Code Review) 07 May '21

07 May '21

Attention is currently required from: Patrick Rudolph. Star Labs has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52798 ) Change subject: soc/mainboard: Add Star Labs labtop series ...................................................................... Patch Set 14: (1 comment) File src/mainboard/starlabs/labtop/Kconfig: https://review.coreboot.org/c/coreboot/+/52798/comment/011b9452_6decbd16 PS14, Line 26: HAVE_IFD_BIN > resolve commented options Shall I just remove them? Comments were only added to stop the build failure for this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/52798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37c74d03d86fb124ed96e45d1bf137eb2ec57251 Gerrit-Change-Number: 52798 Gerrit-PatchSet: 14 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 06:11:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/common/pmclib: Use pmbase functions
by Patrick Georgi (Code Review) 07 May '21

07 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52939 ) Change subject: sb/intel/common/pmclib: Use pmbase functions ...................................................................... sb/intel/common/pmclib: Use pmbase functions Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52939 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/common/pmclib.c 1 file changed, 11 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c index 5bc0ef1..34a449b 100644 --- a/src/southbridge/intel/common/pmclib.c +++ b/src/southbridge/intel/common/pmclib.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootmode.h> #include <stdint.h> #include <acpi/acpi.h> #include <console/console.h> @@ -8,31 +9,24 @@ #include "pmbase.h" #include "pmutil.h" +static void clear_power_state(void) +{ + uint32_t pm1_cnt = read_pmbase32(PM1_CNT); + write_pmbase32(PM1_CNT, pm1_cnt & ~SLP_TYP); +} + int southbridge_detect_s3_resume(void) { - u32 pm1_cnt; - u16 pm1_sts; - int is_s3 = 0; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = read_pmbase16(PM1_STS); - if (pm1_sts & WAK_STS) { - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = read_pmbase32(PM1_CNT); - if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { - /* Clear SLP_TYPE. */ - write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); - is_s3 = 1; - } - } - if (is_s3) { + if (platform_is_resuming()) { + clear_power_state(); if (!acpi_s3_resume_allowed()) { printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n"); return 0; } printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n"); + return 1; } - return is_s3; + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Gerrit-Change-Number: 52939 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/common: Fix platform_is_resuming()
by Patrick Georgi (Code Review) 07 May '21

07 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52930 ) Change subject: sb/intel/common: Fix platform_is_resuming() ...................................................................... sb/intel/common: Fix platform_is_resuming() platform_is_resuming() was using the wrong register (PM1_STS) to figure out if the platform was resuming (PM1_CNT). Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52930 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/common/pmbase.c 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index bbd2c25..d5578fc 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -80,6 +80,10 @@ return acpi_sleep_from_pm1(read_pmbase32(PM1_CNT)); } +/* + * Note that southbridge_detect_s3_resume clears the sleep state, + * so this may not be used reliable throughout romstage. + */ int platform_is_resuming(void) { u16 reg16 = read_pmbase16(PM1_STS); @@ -87,5 +91,5 @@ if (!(reg16 & WAK_STS)) return 0; - return acpi_sleep_from_pm1(reg16) == ACPI_S3; + return acpi_get_sleep_type() == ACPI_S3; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Gerrit-Change-Number: 52930 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021