coreboot-gerrit May 2021

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Change in coreboot[master]: soc/mediatek/mt8195: Add clk_buf driver
by Yu-Ping Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53896 ) Change subject: soc/mediatek/mt8195: Add clk_buf driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Gerrit-Change-Number: 53896 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 08:01:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add i2c driver support
by Yu-Ping Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53894 ) Change subject: soc/mediatek/mt8195: Add i2c driver support ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8195/i2c.c: https://review.coreboot.org/c/coreboot/+/53894/comment/8c39ecd4_b73e84a4 PS1, Line 13: #define I2C_FS_START_CON 0x0 One blank line after this. -- To view, visit https://review.coreboot.org/c/coreboot/+/53894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia26e55512501e9758d7f5543d176730cf30ce03d Gerrit-Change-Number: 53894 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 07 May 2021 07:59:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add mt6360 driver for LDO access
by Yu-Ping Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53893 ) Change subject: soc/mediatek/mt8195: Add mt6360 driver for LDO access ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8195/mt6360.c: https://review.coreboot.org/c/coreboot/+/53893/comment/0713be16_1198c2a9 PS1, Line 74: One space -- To view, visit https://review.coreboot.org/c/coreboot/+/53893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68ca7067f76a67c4e797437593539f8f85909edc Gerrit-Change-Number: 53893 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 07 May 2021 07:57:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Configure eMMC and SDCard
by Yu-Ping Wu (Code Review) 07 May '21

07 May '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53895 ) Change subject: soc/mediatek/mt8195: Configure eMMC and SDCard ...................................................................... Patch Set 1: (6 comments) File src/mainboard/google/cherry/mainboard.c: https://review.coreboot.org/c/coreboot/+/53895/comment/c077bbcd_02fb2e6b PS1, Line 88: MSDC1_GPIO_MODE0_0, MSDC1_GPIO_MODE0_VALUE, > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/53895/comment/10d1d795_20fd5393 PS1, Line 89: MSDC1_GPIO_MODE0_1, MSDC1_GPIO_MODE0_VALUE); > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/53895/comment/5ab42016_a7164ea7 PS1, Line 93: MSDC1_GPIO_MODE1_0, MSDC1_GPIO_MODE1_VALUE, > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/53895/comment/908883ef_f70360fb PS1, Line 94: MSDC1_GPIO_MODE1_1, MSDC1_GPIO_MODE1_VALUE, > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/53895/comment/d73553d2_d93d4caa PS1, Line 95: MSDC1_GPIO_MODE1_2, MSDC1_GPIO_MODE1_VALUE, > code indent should use tabs where possible Please fix. https://review.coreboot.org/c/coreboot/+/53895/comment/d071cbde_f198bf14 PS1, Line 96: MSDC1_GPIO_MODE1_3, MSDC1_GPIO_MODE1_VALUE); > code indent should use tabs where possible Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/53895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed82e860612e8a62f361e60d217280f775ab239 Gerrit-Change-Number: 53895 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 07 May 2021 07:55:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add MMIO support in PCI lib
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53903 ) Change subject: libpayload: Add MMIO support in PCI lib ...................................................................... Patch Set 1: (5 comments) File payloads/libpayload/include/arm64/arch/io.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118692): https://review.coreboot.org/c/coreboot/+/53903/comment/4d884ec5_b6031d67 PS1, Line 154: } void function return statements are not generally useful Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118692): https://review.coreboot.org/c/coreboot/+/53903/comment/a2337465_05c4f2a9 PS1, Line 159: } void function return statements are not generally useful File src/commonlib/include/commonlib/coreboot_tables.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118692): https://review.coreboot.org/c/coreboot/+/53903/comment/70425c3c_9668b313 PS1, Line 332: uint32_t tag; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118692): https://review.coreboot.org/c/coreboot/+/53903/comment/c45b9703_7cfb4669 PS1, Line 333: uint32_t size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118692): https://review.coreboot.org/c/coreboot/+/53903/comment/636a19f1_4534af32 PS1, Line 334: void *config_base; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/53903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Gerrit-Change-Number: 53903 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:41:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... Patch Set 1: (26 comments) File src/soc/qualcomm/sc7280/include/soc/addressmap.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/8c737d51_534a8ad7 PS1, Line 68: #define PCIE1_MEM_SIZE 0x1fd00000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/106a9c27_3332f1eb PS1, Line 69: #define PCIE_MEM_END 0x404fffff please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/9a5444cc_b86629dd PS1, Line 72: #define PCIE_1_QMP_PHY 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/2b81c065_248ecf87 PS1, Line 76: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/178aa946_a387b5cd PS1, Line 18: #define DEV_ID_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/d5c8728d_87c03144 PS1, Line 19: #define CLASS_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/f40b27bd_a26fd94d PS1, Line 20: #define HEADER_SZ 8 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/ca0477ab_ff35e928 PS1, Line 21: #define VEND_ID_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/e10b1773_7082d7d1 PS1, Line 25: #define PCIE_CLASS 0x0a please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/6fb4a493_fb2fe12d PS1, Line 26: #define PCI_MAX_DEV_FN 0x100 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/b067d885_766bc7d4 PS1, Line 41: #define PCIE1_3x2_NUM_LANES 2 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/e95f84f7_76259d79 PS1, Line 57: #define PERST_DELAY_US 1000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/19b2da09_2c580801 PS1, Line 58: #define PCIE_MAX_BARS 6 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/f6eb42e2_1f917d0b PS1, Line 154: #define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/40999bed_803b1c08 PS1, Line 155: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/b902c9db_31854c3c PS1, Line 156: #define PCE1_QPHY_TX0 0x01C0E200 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/1074f8ee_b4da59a1 PS1, Line 157: #define PCE1_QPHY_RX0 0x01C0E400 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/470ff0bd_55935529 PS1, Line 169: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/1259a10f_988cf38d PS1, Line 169: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/969fb0ea_1137d952 PS1, Line 188: #define PCIE_DEV(_bus, _dev, _fn) (0x80000000 | \ Macros with complex values should be enclosed in parentheses File src/soc/qualcomm/sc7280/pcie_host.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/e2616ae6_4c1dda0d PS1, Line 303: pci_ep_cfg_info.config_base = (void*)PCIE1_GEN3x2_CONF; "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/e69fd2c5_437c33cb PS1, Line 459: printk(BIOS_INFO,"pcie ep PERST asserted \n"); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/d2a8149b_f103217e PS1, Line 459: printk(BIOS_INFO,"pcie ep PERST asserted \n"); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/4243c6a1_9e074578 PS1, Line 468: printk(BIOS_NOTICE,"pcie ep PERST desserted\n"); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/c4c9555b_745d6b49 PS1, Line 773: if (vend_id == 0xffff || vend_id == 0x0000) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118691): https://review.coreboot.org/c/coreboot/+/53902/comment/a59ba514_fd463891 PS1, Line 1140: if(!ret) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:40:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add display support for mipi panels
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52662 ) Change subject: sc7180: Add display support for mipi panels ...................................................................... Patch Set 4: (15 comments) File src/mainboard/google/trogdor/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/781599fc_2a85aac4 PS4, Line 101: if(CONFIG(TROGDOR_HAS_MIPI_PANEL)) space required before the open parenthesis '(' File src/soc/qualcomm/sc7180/display/dsi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/ef7ff448_3411ef0a PS4, Line 65: write32(&dsi0->trig_ctrl,DSI_DMA_STREAM1 << 8 | DSI_DMA_TRIGGER_SEL); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/7bc43577_b0138c34 PS4, Line 172: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/c18ce9e6_ecb3a965 PS4, Line 210: printk(BIOS_ERR, Invalid vsprintf pointer extension '%pk' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/cc1a6b5e_bf662135 PS4, Line 281: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/32f48afd_8ec8fd8d PS4, Line 289: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/b343f3a0_a203635b PS4, Line 292: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/75a22199_a878f056 PS4, Line 299: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/01e9b2d1_98c88a4f PS4, Line 302: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/abba0184_bb9a5711 PS4, Line 319: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/ddcf68c2_bdfb6b18 PS4, Line 322: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_DMA_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/798c871a_06183c2f PS4, Line 325: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_MDP_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/4710279f_71bad8b2 PS4, Line 328: setbits32(&dsi0->int_ctrl,DSI_VIDEO_MODE_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/88c86c84_ce5eb6ac PS4, Line 333: setbits32(&dsi0->int_ctrl,DSI_ERROR_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118688): https://review.coreboot.org/c/coreboot/+/52662/comment/04e154a0_40e8ba8d PS4, Line 343: if(!pinfo && !pinfo->init_cmd) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/52662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Gerrit-Change-Number: 52662 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:38:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode HACK
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode HACK ...................................................................... Patch Set 34: (1 comment) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118684): https://review.coreboot.org/c/coreboot/+/50586/comment/da7c67a0_5eb16e95 PS34, Line 499: while (1) suspect code indent for conditional statements (16, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 34 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:37:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add GSI FW download support
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52371 ) Change subject: sc7280: Add GSI FW download support ...................................................................... Patch Set 6: (11 comments) File src/soc/qualcomm/sc7280/include/soc/qupv3_config.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/20103772_c1d1651d PS6, Line 77: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/ce1918c5_d43fe879 PS6, Line 79: uint32_t iram_dword1; /* word 1 of a single IRAM firmware entry */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/4fa94d80_62438b33 PS6, Line 83: { open brace '{' following struct go on the same line File src/soc/qualcomm/sc7280/qupv3_config.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/1eb45b9a_51b52a85 PS6, Line 204: write32(&regs->gsi_periph_base_lsb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/0d58d7a2_932834d0 PS6, Line 205: write32(&regs->gsi_periph_base_msb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/3064244c_0677d92b PS6, Line 210: if (fwIep[i].offset < GSI_REG_BASE_SIZE) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/4a6e86eb_fa2849c7 PS6, Line 221: memcpy((&regs->gsi_inst_ramn),(void *)fwIRam, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/94e0a1b8_baf8fc25 PS6, Line 223: setbits_le32(&regs->gsi_mcs_cfg, GSI_MCS_CFG_MCS_ENABLE_BMSK ); space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/2cba9d84_3211f5af PS6, Line 224: setbits_le32(&regs->gsi_cfg, GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK | GSI_CFG_GSI_ENABLE_BMSK); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/c046af81_aff75cdd PS6, Line 226: write32(&regs->gsi_ee_n_scratch_0_addr,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118679): https://review.coreboot.org/c/coreboot/+/52371/comment/475cad8e_1262edaf PS6, Line 227: write32(&regs->ee_n_gsi_ee_generic_cmd,0x81); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/52371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b966a6a074fc43c62d2639da9cf68b083cc7319 Gerrit-Change-Number: 52371 Gerrit-PatchSet: 6 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 07:34:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: cpucp loading changes
by build bot (Jenkins) (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: cpucp loading changes ...................................................................... Patch Set 33: (42 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/6c7b783c_f68d929b PS33, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/987f5851_302274f4 PS33, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/707bbc5d_9ca6a794 PS33, Line 16: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/ac08faaf_6af0ead4 PS33, Line 16: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/a00f7a1e_d049eb87 PS33, Line 18: /* allow NS access to EPSS memory*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/6e5c03ea_2fabc749 PS33, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/9e7e47b6_37ee2f8b PS33, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/8dc10c53_83a9a037 PS33, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/89b8b5fe_775d78a0 PS33, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/15817128_44548fa0 PS33, Line 22: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/c5a74c45_a04ade79 PS33, Line 22: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/a123f5f7_7ee84314 PS33, Line 24: /* Enable subsystem clock. Required for CPUCP PDMEM access*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/1878b7cb_f6b7c53c PS33, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/d0c3e98e_f45ba42d PS33, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/265d164a_df99f19d PS33, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/5a93c685_eeb7674d PS33, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/20b3cee5_2346c83c PS33, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/f1e1c514_d34a6e67 PS33, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/0e9fabe8_bd1c00f0 PS33, Line 32: bool cpucp_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/a8f34120_e115e6a0 PS33, Line 32: bool cpucp_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/0333eb58_27e12b9d PS33, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/e9ef9202_1828abd9 PS33, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/0e3a4c7c_988a5dec PS33, Line 35: struct prog cpucp_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/66907869_5d3ce9d6 PS33, Line 35: struct prog cpucp_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/aa1d060d_8cd9804b PS33, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/96352b7e_5b2099c7 PS33, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/50e2a228_4f2d5f4e PS33, Line 38: cpucp_prepare(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/615995ba_dfbc813b PS33, Line 38: cpucp_prepare(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/128f6df4_fd3a2363 PS33, Line 40: if (prog_locate(&cpucp_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/cd7a176c_e4911bae PS33, Line 40: if (prog_locate(&cpucp_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/cb9b0a55_5c9d9b68 PS33, Line 41: die("SOC imagpe: CPUCP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/ae3fcb7a_599ccaa1 PS33, Line 41: die("SOC imagpe: CPUCP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/3cfade49_6e8854d8 PS33, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/3c1a55a8_2fc0279f PS33, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/a9bae3d8_b8b3e239 PS33, Line 44: if (!cpucp_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/3c63050b_4fdcc192 PS33, Line 44: if (!cpucp_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/94b3f351_f984fc41 PS33, Line 45: die("SOC image: CPUCP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/5c55eb52_379c9657 PS33, Line 45: die("SOC image: CPUCP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/cdc3b6d8_5d18002a PS33, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/9b36fa85_1d460284 PS33, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/41f7cda0_ad61e7e4 PS33, Line 20: REGION_SIZE(dram_cpucp) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118671): https://review.coreboot.org/c/coreboot/+/49768/comment/2fe009a7_b9044dbd PS33, Line 20: REGION_SIZE(dram_cpucp) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 33 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 07:28:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021