coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
by Michał Żygowski (Code Review) 07 May '21

07 May '21

Attention is currently required from: Felix Held, Piotr Król. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52759 ) Change subject: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy ...................................................................... Patch Set 1: (1 comment) File src/mainboard/pcengines/apu2/OemCustomize.c: https://review.coreboot.org/c/coreboot/+/52759/comment/28563345_1ee44229 PS1, Line 92: if (get_spd_offset()) > my comment was about this call https://review.coreboot. […] Ahh this one. Yes, true. it shall be fixed to either read SPD from index 0 or 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I010645f53b404341895d0545855905e81c89165e Gerrit-Change-Number: 52759 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 07 May 2021 11:08:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Michał Żygowski, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52759 ) Change subject: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy ...................................................................... Patch Set 1: (1 comment) File src/mainboard/pcengines/apu2/OemCustomize.c: https://review.coreboot.org/c/coreboot/+/52759/comment/eea03367_eb9aeee2 PS1, Line 92: if (get_spd_offset()) > Based on the smbios_system_sku function in mainboard. […] my comment was about this call https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… the code here seems to be correct to me, but the line i linked probably has the problem i described -- To view, visit https://review.coreboot.org/c/coreboot/+/52759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I010645f53b404341895d0545855905e81c89165e Gerrit-Change-Number: 52759 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 07 May 2021 11:06:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE
by Hung-Te Lin (Code Review) 07 May '21

07 May '21

Attention is currently required from: Rex-BC Chen. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53898 ) Change subject: soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWARE ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: make_helpers/plat_helpers.mk:32: *** "Error: Invalid platform. The following platforms are available: We need to uprev the ATF in coreboot 3rdparty/ submodule before we can merge this. @yupingso you may need to check with jwerner@ for how to do that.... (not the one in cros repo) -- To view, visit https://review.coreboot.org/c/coreboot/+/53898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Gerrit-Change-Number: 53898 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 May 2021 10:22:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
by Hung-Te Lin (Code Review) 07 May '21

07 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52925 ) Change subject: soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache ...................................................................... soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/mmu_operations.c M src/soc/mediatek/mt8195/soc.c 3 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 796c335..f848f7b 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += emi.c ramstage-y += ../common/flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c new file mode 100644 index 0000000..7018093 --- /dev/null +++ b/src/soc/mediatek/mt8195/mmu_operations.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/mcucfg.h> +#include <soc/mmu_operations.h> +#include <soc/symbols.h> + +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) +DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) + +void mtk_soc_disable_l2c_sram(void) +{ + unsigned long v; + + SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_EN, 0); + dsb(); + + __asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v)); + v |= (0xf << 4); + __asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v)); + dsb(); + + do { + __asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v)); + } while (((v >> 0x4) & 0xf) != 0xf); + + SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0, + MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); + dsb(); +} diff --git a/src/soc/mediatek/mt8195/soc.c b/src/soc/mediatek/mt8195/soc.c index af28dd4..4c98a66 100644 --- a/src/soc/mediatek/mt8195/soc.c +++ b/src/soc/mediatek/mt8195/soc.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <soc/emi.h> +#include <soc/mmu_operations.h> #include <symbols.h> static void soc_read_resources(struct device *dev) @@ -11,6 +12,7 @@ static void soc_init(struct device *dev) { + mtk_mmu_disable_l2c_sram(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Gerrit-Change-Number: 52925 Gerrit-PatchSet: 5 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/cherry: configure GPIOs
by Hung-Te Lin (Code Review) 07 May '21

07 May '21

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52924 ) Change subject: mb/google/cherry: configure GPIOs ...................................................................... mb/google/cherry: configure GPIOs Configure Chromebook specific GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/cherry/bootblock.c M src/mainboard/google/cherry/chromeos.c A src/mainboard/google/cherry/gpio.h 3 files changed, 43 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index 6f61a82..adb87d0 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -4,6 +4,8 @@ #include <device/mmio.h> #include <soc/gpio.h> +#include "gpio.h" + struct pad_func { u8 pin_id; u8 func; @@ -34,4 +36,5 @@ void bootblock_mainboard_init(void) { nor_set_gpio_pinmux(); + setup_chromeos_gpios(); } diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 3f0937f..f606ba3 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -2,10 +2,31 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> +#include <gpio.h> + +#include "gpio.h" + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input_pullup(GPIO_EC_AP_INT); + gpio_input_pullup(GPIO_SD_CD); + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_GSC_AP_INT); + gpio_output(GPIO_EN_SPK, 0); + gpio_output(GPIO_RESET, 0); +} void fill_lb_gpios(struct lb_gpios *gpios) { - + struct lb_gpio chromeos_gpios[] = { + {GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"}, + {GPIO_SD_CD.id, ACTIVE_LOW, -1, "SD card detect"}, + {GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"}, + {GPIO_GSC_AP_INT.id, ACTIVE_LOW, -1, "TPM interrupt"}, + {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_recovery_mode_switch(void) diff --git a/src/mainboard/google/cherry/gpio.h b/src/mainboard/google/cherry/gpio.h new file mode 100644 index 0000000..28e1186 --- /dev/null +++ b/src/mainboard/google/cherry/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CHERRY_GPIO_H__ +#define __MAINBOARD_GOOGLE_CHERRY_GPIO_H__ + +#include <soc/gpio.h> + +#define GPIO_EC_AP_INT GPIO(GPIO_04) +#define GPIO_WP GPIO(GPIO_05) +#define GPIO_SD_CD GPIO(I2SO1_D1) +#define GPIO_EC_IN_RW GPIO(DGI_D10) +#define GPIO_GSC_AP_INT GPIO(DGI_D11) +#define GPIO_EN_SPK GPIO(UART1_RTS) +#define GPIO_RESET GPIO(UART1_CTS) + +void setup_chromeos_gpios(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/52924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Gerrit-Change-Number: 52924 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/console: Fix FSP Notify phase postcodes discrepancy
by Subrata Banik (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52894 ) Change subject: include/console: Fix FSP Notify phase postcodes discrepancy ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Any further review @Angel/Furquan? -- To view, visit https://review.coreboot.org/c/coreboot/+/52894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Gerrit-Change-Number: 52894 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 10:09:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create chronicler variant
by Sheng-Liang Pan (Code Review) 07 May '21

07 May '21

Attention is currently required from: Tim Wawrzynczak, Paul Fagerburg, Nick Vaccaro, YH Lin. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53907 ) Change subject: mb/google/volteer: Create chronicler variant ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/53907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018 Gerrit-Change-Number: 53907 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 10:09:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN
by Subrata Banik (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52947 ) Change subject: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Any further review @Angel/Furquan? -- To view, visit https://review.coreboot.org/c/coreboot/+/52947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Gerrit-Change-Number: 52947 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 10:09:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Subrata Banik (Code Review) 07 May '21

07 May '21

Attention is currently required from: Subrata Banik, Nico Huber, Furquan Shaikh, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Any further review @Angel/Furquan? -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 10:09:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create chronicler variant
by Sheng-Liang Pan (Code Review) 07 May '21

07 May '21

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53907 ) Change subject: mb/google/volteer: Create chronicler variant ...................................................................... mb/google/volteer: Create chronicler variant Create the chronicler variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:187318819 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_CHRONICLER Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018 --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h A src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h A src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc A src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/chronicler/overridetree.cb 8 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/53907/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index de301f1..4f42f42 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -107,6 +107,7 @@ default "Drobit" if BOARD_GOOGLE_DROBIT default "Copano" if BOARD_GOOGLE_COPANO default "Collis" if BOARD_GOOGLE_COLLIS + default "Chronicler" if BOARD_GOOGLE_CHRONICLER config MAX_CPUS int @@ -152,6 +153,7 @@ default "drobit" if BOARD_GOOGLE_DROBIT default "copano" if BOARD_GOOGLE_COPANO default "collis" if BOARD_GOOGLE_COLLIS + default "chronicler" if BOARD_GOOGLE_CHRONICLER config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 4b580ad..d392352 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -87,3 +87,7 @@ config BOARD_GOOGLE_COLLIS bool "-> Collis" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_CHRONICLER + bool "-> Chronicler" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h b/src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h b/src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc b/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt new file mode 100644 index 0000000..e4258b5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/volteer/variants/chronicler/overridetree.cb b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/chronicler/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/53907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018 Gerrit-Change-Number: 53907 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021