coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52917 ) Change subject: soc/amd/common/fsp/pci: Implement acpigen_write_pci_PRT ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: not done yet with the review File src/soc/amd/common/fsp/pci/acpi_prt.c: https://review.coreboot.org/c/coreboot/+/52917/comment/8e97f77c_7c4a15a4 PS3, Line 22: acpigen_write_PRT_source_entry acpigen_write_PRT_GSI_entry -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 14:05:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Andy Pont (Code Review) 07 May '21

07 May '21

Attention is currently required from: Patrick Rudolph. Andy Pont has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... Patch Set 7: (1 comment) File src/ec/starlabs/it8987/ec.h: https://review.coreboot.org/c/coreboot/+/52797/comment/4d42b72e_d55c6702 PS6, Line 11: 0x4e > shouldn't that be provided by mainboard code as it could be 0x2e as well? The datasheet for the IT8987 does allow 0x2e/0x2f and 0x4e/0x4f as address/data register pairs. The working setting is controlled through the BADRSEL register which is only accessible from the EC domain and therefore is controlled by the binary blob EC firmware. All existing versions of the EC firmware use 0x4e/0x4f. -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 7 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 14:02:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec: Add Star Labs ITE 8987E support
by Star Labs (Code Review) 07 May '21

07 May '21

Attention is currently required from: Patrick Rudolph. Star Labs has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52797 ) Change subject: ec: Add Star Labs ITE 8987E support ...................................................................... Patch Set 7: (3 comments) File .tmpconfig.lintn90hoF: PS6: > seems accidentally added Done File src/ec/starlabs/it8987/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/52797/comment/557ab63b_f79bd84f PS6, Line 79: Not > remove dead code Done File src/ec/starlabs/it8987/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/52797/comment/b404b6ec_cbda3ef0 PS6, Line 169: SMB2 > unused code Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1967f7c4a7e3cab714f22844bf36749e0c9652b6 Gerrit-Change-Number: 52797 Gerrit-PatchSet: 7 Gerrit-Owner: Star Labs <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 14:02:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/pcengines/apu1: Disable memory bank interleaving
by Patrick Georgi (Code Review) 07 May '21

07 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52779 ) Change subject: mb/pcengines/apu1: Disable memory bank interleaving ...................................................................... mb/pcengines/apu1: Disable memory bank interleaving Bank interleaving does not work on this platform, disable it. AmdInitPost returns success thanks to this setting. TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/52779 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/pcengines/apu1/OemCustomize.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Krystian Hebel: Looks good to me, but someone else must approve diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index d6edf03..254947c 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -101,4 +101,6 @@ void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; + /* Bank interleaving is not supported on this platform */ + InitPost->MemConfig.EnableBankIntlv = FALSE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca Gerrit-Change-Number: 52779 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
by Arthur Heymans (Code Review) 07 May '21

07 May '21

Attention is currently required from: Angel Pons, Arthur Heymans, Alexander Couzens, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52942 ) Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/socket_p/Kconfig: https://review.coreboot.org/c/coreboot/+/52942/comment/c5c32718_84e6514c PS1, Line 16: default 0x10000 > CPU_INTEL_SOCKET_BGA956 and CPU_INTEL_SOCKET_M use 0x8000 here, and are never used with NO_CBFS_MCACHE. I'd simply drop `select NO_CBFS_MCACHE` from t400. config.lenovo_t400_vboot_and_debug fails to build then :-/ I'm pretty sure cache won't be an issue but I can also strip down that config. Any thoughts? Obviously t400 should not miss out on cbfs_mcache because of a probably not booting debug buildtest. -- To view, visit https://review.coreboot.org/c/coreboot/+/52942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772 Gerrit-Change-Number: 52942 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 13:15:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Zhuohao Lee (Code Review) 07 May '21

07 May '21

Attention is currently required from: Tim Wawrzynczak, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/53908 to look at the new patch set (#2). Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... mb/google/volteer: adjust the size for RO/RW mcache The mcache is overflowed in the latest build. In order to fix the mcache overflow, we increase the mcache size to 0x4000 and adjust the percentage to 50% for the ro/rw mcache. This change is for all of the volteer variants as we see many of the volteer variants which use the latest bios having the mcache overflow issue. BUG=b:187095474, b:187095765, b:187234881, b:162052593 TEST=no mcache overflow in the bios log Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/53908/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Zhuohao Lee (Code Review) 07 May '21

07 May '21

Zhuohao Lee has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53908 ) Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... mb/google/volteer: adjust the size for RO/RW mcache The mcache is overflowed in the latest build. In order to fix the mcache overflow, we increase the mcache size to 0x4000 and adjust the percentage to 50% for the ro/rw mcache. This change is for all of the volteer variants as we see many of the volteer variants which use the latest bios having the mcache overflow issue. BUG=b:187095474, b:187095765, b:187234881, b:162052593 TEST=no mcache overflow in the bios log Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 --- M src/mainboard/google/volteer/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/53908/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index de301f1..bf14a82 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -157,4 +157,12 @@ bool default n +config CBFS_MCACHE_RW_PERCENTAGE + int + default 50 + +config CBFS_MCACHE_SIZE + hex + default 0x4000 + endif # BOARD_GOOGLE_BASEBOARD_VOLTEER -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52759 ) Change subject: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy ...................................................................... mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy Bank interleaving does not work on this platform, disable it. Additionally enable ECC feature on SKUs supporting it. AmdIntPost returns success thanks to these settings. TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after AmdInitPost Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I010645f53b404341895d0545855905e81c89165e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/pcengines/apu2/OemCustomize.c 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6e6b5a2..95af6ef 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -3,6 +3,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/state_machine.h> +#include "gpio_ftns.h" + static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -78,3 +80,17 @@ InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CpbMode = CpbModeAuto; } + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* + * Bank interleaving does not work on this platform. + * Disable it so AGESA will return success. + */ + Post->MemConfig.EnableBankIntlv = FALSE; + /* 4GB variants have ECC */ + if (get_spd_offset()) + Post->MemConfig.EnableEccFeature = TRUE; + else + Post->MemConfig.EnableEccFeature = FALSE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I010645f53b404341895d0545855905e81c89165e Gerrit-Change-Number: 52759 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Michał Żygowski, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52759 ) Change subject: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/pcengines/apu2/OemCustomize.c: https://review.coreboot.org/c/coreboot/+/52759/comment/33756dde_7e02a16d PS1, Line 92: if (get_spd_offset()) > Ahh this one. Yes, true. […] yep. since it's unrelated to this patch, just do that in a follow-up; feel free to add me as reviewer there -- To view, visit https://review.coreboot.org/c/coreboot/+/52759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I010645f53b404341895d0545855905e81c89165e Gerrit-Change-Number: 52759 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 07 May 2021 12:46:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt/Makefile.inc: Use variables for hash alg
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Martin Roth, Christian Walter, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51975 ) Change subject: security/intel/cbnt/Makefile.inc: Use variables for hash alg ...................................................................... Patch Set 2: Code-Review+1 (3 comments) File src/security/intel/cbnt/Makefile.inc: https://review.coreboot.org/c/coreboot/+/51975/comment/95b9d497_a5fd4975 PS2, Line 5: ® Jenkins hates the ® for some reason. https://review.coreboot.org/c/coreboot/+/51975/comment/e1ac08aa_c2642fba PS2, Line 6: 558294 document number 558294 https://review.coreboot.org/c/coreboot/+/51975/comment/b544a08e_72f3d076 PS2, Line 8: PK_HASH_ALG_SHA1:=4 nit: keep the values numerically sorted? -- To view, visit https://review.coreboot.org/c/coreboot/+/51975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4113b1496e99c10017fc1d85a4acbbc16d32ea41 Gerrit-Change-Number: 51975 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 07 May 2021 12:33:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021