coreboot-gerrit May 2021

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Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Report missing resources
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Michał Żygowski, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52927 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Report missing resources ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/52927/comment/61d87d61_aceab423 PS3, Line 256: * 0xc0000 - 0xcffff: VGA OPROM is it intended that the d segment isn't listed here? -- To view, visit https://review.coreboot.org/c/coreboot/+/52927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia57ab026218f4aae0a98c2081412c4a9ebb7f57a Gerrit-Change-Number: 52927 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 15:16:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation
by Nico Huber (Code Review) 07 May '21

07 May '21

Attention is currently required from: Michał Żygowski, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 ) Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ...................................................................... Patch Set 4: (14 comments) Patchset: PS4: Thanks for splitting the patch. It's still a bit big, though. Took me almost 3 hours to read through the first two platforms (fam14 and fam15tn). The new functions look similar enough to extract common code. What generally works well to get a break during review is to add common code in one commit, and then update the individual platforms one-by-one in separate commits. The code changes look sane, alas the comments and the commit message don't. Without kowing further details, it seems possible that the change of the granularity for the newer platforms results in further problems. And this change is not even mentioned in the commit message. IMHO, a simple comment like /* The upper half of each register provides the DRAM base/limit in 16MiB steps. */ could replace all the error-prone and redundant (considering that the documentation is public) comments about bit offsets. I did not see any overflowing shift operations. Though, it looks like the original code treated the limit as exclusive, while it wasn't. File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/4260891c_854d804c PS3, Line 553: limitk = (resource_t) (((u64) d.mask << 8) | 0xFFFFFF); I don't see any overflow here. Can you provide before/after logs what changed here effectively? https://review.coreboot.org/c/coreboot/+/52922/comment/55dbadbc_98a37bf1 PS3, Line 573: sizek = limitk - 768; I think this was missing the `+ 1`. Which is implicitly fixed by making `limitk` exclusive. https://review.coreboot.org/c/coreboot/+/52922/comment/90ad0e13_ab396588 PS3, Line 581: limitk > Same off-by-one here, I assume. https://review.coreboot.org/c/coreboot/+/52922/comment/58c7e7f7_b01727be PS3, Line 115: [39:24] at [31:16] BKDG says [35:24] at [27:16]. This would also be what the code masks below. https://review.coreboot.org/c/coreboot/+/52922/comment/b66772e9_708f5cc5 PS3, Line 119: {DramBase[35:24], 00_0000h} <= address[35:0] How to calculate an 8 from this? I'm guessing by taking the masked bits into account. But if I have to look at the code to derive it, what's the comment worth? Actually the comment above ("[39:24] at [31:16]") seems to explain it better. Well, it would, if the code wouldn't conflict that comment. https://review.coreboot.org/c/coreboot/+/52922/comment/c9645fc7_61012e42 PS3, Line 120: convert to KiB by shifting 10 bits left Please use `/ KiB` (commonlib/helpers.h) instead. https://review.coreboot.org/c/coreboot/+/52922/comment/ec6da4ba_a2f9f67a PS3, Line 127: [39:24] at [31:16] BKDG mentions [39:36] as 0, and the mask below only covers the other bits. https://review.coreboot.org/c/coreboot/+/52922/comment/7cec83bb_1253d2a8 PS3, Line 129: byte kilobyte? https://review.coreboot.org/c/coreboot/+/52922/comment/38767fb8_1238ad07 PS3, Line 129: *limitk += 1; // round up last byte Nit, if this was `+= 16*MiB/KiB`, no or-mask would be needed above. Mentioning the 16MiB granularity at the start of the function would probably make things easier to follow. File src/northbridge/amd/agesa/family15tn/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/064b212b_0e1e1176 PS3, Line 47: mask out DramMask [26:24] too Any idea why the original code did this? It was basically forcing 128MiB granularity. https://review.coreboot.org/c/coreboot/+/52922/comment/4140edf2_d8402fe9 PS3, Line 710: sizek = limitk - basek; This seems off by one granularity step (128MiB). Probably the actual problem? https://review.coreboot.org/c/coreboot/+/52922/comment/e7882fd9_8ae57016 PS3, Line 123: = *basek | Nit, `|=`. File src/northbridge/amd/pi/00730F01/northbridge.c: https://review.coreboot.org/c/coreboot/+/52922/comment/8b2532f0_3795c977 PS3, Line 135: } This looks familiar. If it's the same function again, please consider to not add more redundant code. `common/` directories are easily added. -- To view, visit https://review.coreboot.org/c/coreboot/+/52922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Gerrit-Change-Number: 52922 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 07 May 2021 15:15:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cezanne/psp_verstage: update SRAM address
by Raul Rangel (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53904 ) Change subject: cezanne/psp_verstage: update SRAM address ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9 Gerrit-Change-Number: 53904 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 15:14:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Fix TPM setting in devicetree
by Raul Rangel (Code Review) 07 May '21

07 May '21

Attention is currently required from: Ivy Jian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53891 ) Change subject: mb/google/mancomb: Fix TPM setting in devicetree ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728da76cee0c92c29df4c6ee8bfb4cd07a6366c4 Gerrit-Change-Number: 53891 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 May 2021 15:13:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create volet variant
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52871 ) Change subject: mb/google/volteer: Create volet variant ...................................................................... mb/google/volteer: Create volet variant Create the volet variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:186334008 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLET Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/volet/include/variant/ec.h A src/mainboard/google/volteer/variants/volet/include/variant/gpio.h A src/mainboard/google/volteer/variants/volet/memory/Makefile.inc A src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt A src/mainboard/google/volteer/variants/volet/overridetree.cb 8 files changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve Sheng-Liang Pan: Looks good to me, but someone else must approve Paul Fagerburg: Looks good to me, approved diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index de301f1..bdfb6da 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -107,6 +107,7 @@ default "Drobit" if BOARD_GOOGLE_DROBIT default "Copano" if BOARD_GOOGLE_COPANO default "Collis" if BOARD_GOOGLE_COLLIS + default "Volet" if BOARD_GOOGLE_VOLET config MAX_CPUS int @@ -152,6 +153,7 @@ default "drobit" if BOARD_GOOGLE_DROBIT default "copano" if BOARD_GOOGLE_COPANO default "collis" if BOARD_GOOGLE_COLLIS + default "volet" if BOARD_GOOGLE_VOLET config VARIANT_HAS_MIPI_CAMERA bool diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 4b580ad..14062a9 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -87,3 +87,7 @@ config BOARD_GOOGLE_COLLIS bool "-> Collis" select BOARD_GOOGLE_BASEBOARD_VOLTEER + +config BOARD_GOOGLE_VOLET + bool "-> Volet" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/volet/include/variant/ec.h b/src/mainboard/google/volteer/variants/volet/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/volet/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volet/include/variant/gpio.h new file mode 100644 index 0000000..b5fa8c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/include/variant/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +/* Copied from baseboard and may need to change for the new variant. */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +#endif diff --git a/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt new file mode 100644 index 0000000..e4258b5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/volteer/variants/volet/overridetree.cb b/src/mainboard/google/volteer/variants/volet/overridetree.cb new file mode 100644 index 0000000..32204c5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/tigerlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/52871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589 Gerrit-Change-Number: 52871 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Force resets to be cold
by Marshall Dawson (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52982 ) Change subject: soc/amd/cezanne: Force resets to be cold ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52982/comment/dc463a9b_f0ec6025 PS1, Line 10: AGESA has cleared it in : FSP-S. > That's pretty funny. […] Now I'm not seeing it clear either. File src/soc/amd/cezanne/reset.c: https://review.coreboot.org/c/coreboot/+/52982/comment/3a1694f4_db65a65f PS1, Line 10: /* TODO: is NCP_ERR still valid? It appears reserved and always 0xff. b/184281092 */ > ppr says that's it's still valid; see LEGACYIOx000000F0 (FCH::IO::NCP_ERROR) […] Ack. I'd experimented a little with HDT, including before the FSP call, and could never see the register behaving correctly. We can check whether the PSP writes the register, although I can't think of a legitimate reason it would. -- To view, visit https://review.coreboot.org/c/coreboot/+/52982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Gerrit-Change-Number: 52982 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 14:53:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: psp_verstage: remove not-implemented files for cezanne
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53905 ) Change subject: psp_verstage: remove not-implemented files for cezanne ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/psp_verstage/Makefile.inc: https://review.coreboot.org/c/coreboot/+/53905/comment/eb412e84_458b28f4 PS1, Line 17: ifneq ($(CONFIG_SOC_AMD_CEZANNE),y) i don't like having checks for certain SoCs in the common code, since this will probably cause some issues when adding new SoCs. if the code is specific to picasso, i'd either move it back to the picasso folder or if it isn't picasso-specific have some kconfig options to select the different interface revisions like i did for example in soc/amc/common/block/psp -- To view, visit https://review.coreboot.org/c/coreboot/+/53905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b Gerrit-Change-Number: 53905 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 14:53:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Force resets to be cold
by Marshall Dawson (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52982 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Force resets to be cold ...................................................................... soc/amd/cezanne: Force resets to be cold Cezanne must use cold resets. Change the warm reset request to always use cold. BUG=b:184281092 TEST=Majolica successfully resets using 0xcf9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 --- M src/soc/amd/cezanne/reset.c 1 file changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/52982/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Gerrit-Change-Number: 52982 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: amd/cezanne: verify transfer buffer in bootblock
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Kangheui Won. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52965 ) Change subject: amd/cezanne: verify transfer buffer in bootblock ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: not sure if you also want to add the boot_with_psp_timestamp call in bootblock_c_entry that also depends on VBOOT_STARTS_BEFORE_BOOTBLOCK. probably something for a separate patch though -- To view, visit https://review.coreboot.org/c/coreboot/+/52965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c470b156944b50e581dcdee47b196f46b0993f3 Gerrit-Change-Number: 52965 Gerrit-PatchSet: 4 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 14:49:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Create chronicler variant
by Paul Fagerburg (Code Review) 07 May '21

07 May '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Sheng-Liang Pan, YH Lin. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53907 ) Change subject: mb/google/volteer: Create chronicler variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018 Gerrit-Change-Number: 53907 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 14:49:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021