coreboot-gerrit May 2021

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Change in coreboot[master]: soc/amd/picasso,common: move ALIB DPTC IDs to common code
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53917 ) Change subject: soc/amd/picasso,common: move ALIB DPTC IDs to common code ...................................................................... soc/amd/picasso,common: move ALIB DPTC IDs to common code These parameter IDs are defined in the AGESA Interface specification #55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes the names more consistent. TEST=Timeless build for Mandolin results in identical binary. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04 --- M src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/root_complex.c 2 files changed, 32 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/53917/1 diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h index a59ba8b..e11b1ae 100644 --- a/src/soc/amd/common/block/include/amdblocks/alib.h +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -6,4 +6,16 @@ #define ALIB_FUNCTION_REPORT_AC_DC_STATE 0x1 #define ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG 0xc +#ifndef __ACPI__ + +/* parameter IDs for the ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG function */ +enum alib_dptc_parameter_ids { + ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID = 0x3, + ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID = 0x5, + ALIB_DPTC_FAST_PPT_LIMIT_ID = 0x6, + ALIB_DPTC_SLOW_PPT_LIMIT_ID = 0x7, +}; + +#endif /* !__ACPI__ */ + #endif /* AMD_COMMON_ALIB_H */ diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 932ca76..c0b444f 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -18,13 +18,6 @@ #include <soc/iomap.h> #include "chip.h" -enum { - THERMAL_CONTROL_LIMIT_ID = 0x3, - SUSTAINED_POWER_LIMIT_PARAM_ID = 0x5, - FAST_PPT_LIMIT_PARAM_ID = 0x6, - SLOW_PPT_LIMIT_PARAM_ID = 0x7, -}; - #define DPTC_TOTAL_UPDATE_PARAMS 4 struct dptc_param { @@ -38,27 +31,27 @@ } __packed; #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ - { \ - .size = sizeof(struct dptc_input), \ - .params = { \ - { \ - .id = THERMAL_CONTROL_LIMIT_ID, \ - .value = _thermctllmit, \ - }, \ - { \ - .id = SUSTAINED_POWER_LIMIT_PARAM_ID, \ - .value = _sustained, \ - }, \ - { \ - .id = FAST_PPT_LIMIT_PARAM_ID, \ - .value = _fast, \ - }, \ - { \ - .id = SLOW_PPT_LIMIT_PARAM_ID, \ - .value = _slow, \ - }, \ + { \ + .size = sizeof(struct dptc_input), \ + .params = { \ + { \ + .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ + .value = _thermctllmit, \ }, \ - } + { \ + .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ + .value = _sustained, \ + }, \ + { \ + .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ + .value = _fast, \ + }, \ + { \ + .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ + .value = _slow, \ + }, \ + }, \ + } /* * * +--------------------------------+ -- To view, visit https://review.coreboot.org/c/coreboot/+/53917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04 Gerrit-Change-Number: 53917 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/root_complex: move DPTC_TOTAL_UPDATE_PARAMS out of enum
by Felix Held (Code Review) 07 May '21

07 May '21

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Change in coreboot[master]: soc/amd: factor out ACPI ALIB function numbers to common code
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53915 ) Change subject: soc/amd: factor out ACPI ALIB function numbers to common code ...................................................................... soc/amd: factor out ACPI ALIB function numbers to common code The ACPI ALIB function numbers are defined in the AMD Generic Encapsulated Software Architecture (AGESA™) Interface Specification (document #55483). TEST=Timeless build stays the same for Mandolin (Picasso) and Gardenia (Stoneyridge). Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161 --- A src/soc/amd/common/block/include/amdblocks/alib.h M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 4 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/53915/1 diff --git a/src/soc/amd/common/block/include/amdblocks/alib.h b/src/soc/amd/common/block/include/amdblocks/alib.h new file mode 100644 index 0000000..a59ba8b --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/alib.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_COMMON_ALIB_H +#define AMD_COMMON_ALIB_H + +#define ALIB_FUNCTION_REPORT_AC_DC_STATE 0x1 +#define ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG 0xc + +#endif /* AMD_COMMON_ALIB_H */ diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 294d89f..869602c 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/alib.h> + /* * Wrapper method that calls ALIB function 1 to report current AC/DC state. */ @@ -23,7 +25,7 @@ F1DA = \PWRS ^ 1 Printf ("ALIB call: func 1 params %o", Local0) - \_SB.ALIB (1, Local0) + \_SB.ALIB (ALIB_FUNCTION_REPORT_AC_DC_STATE, Local0) } Method (PNOT) diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 292ee20..47b3a43 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -2,6 +2,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> +#include <amdblocks/alib.h> #include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> #include <arch/ioapic.h> @@ -18,7 +19,6 @@ #include "chip.h" enum { - ALIB_DPTCI_FUNCTION_ID = 0xc, THERMAL_CONTROL_LIMIT_ID = 0x3, SUSTAINED_POWER_LIMIT_PARAM_ID = 0x5, FAST_PPT_LIMIT_PARAM_ID = 0x6, @@ -196,7 +196,7 @@ /* \_SB.ALIB(0xc, buf_name) */ acpigen_emit_namestring("\\_SB.ALIB"); - acpigen_write_integer(ALIB_DPTCI_FUNCTION_ID); + acpigen_write_integer(ALIB_FUNCTION_DYNAMIC_POWER_THERMAL_CONFIG); acpigen_emit_namestring(buf_name); } diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 4580b77..78ce889 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/alib.h> + External(\_SB.ALIB, MethodObj) /* System Bus */ @@ -142,7 +144,7 @@ F1SZ = 3 F1DA= \PWRS - \_SB.ALIB(1, F1BF) + \_SB.ALIB(ALIB_FUNCTION_REPORT_AC_DC_STATE, F1BF) } /* End Method(_SB._INI) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I290ef0db32c65ebb2bbbe4f65db4df772b884161 Gerrit-Change-Number: 53915 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Force resets to be cold
by Marshall Dawson (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52982 to look at the new patch set (#3). Change subject: soc/amd/cezanne: Force resets to be cold ...................................................................... soc/amd/cezanne: Force resets to be cold Cezanne must use cold resets. Change the warm reset request to always set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power cycles, set it early for good measure. BUG=b:184281092 TEST=Majolica successfully resets using 0xcf9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 --- M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/reset.c 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/52982/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Gerrit-Change-Number: 52982 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52947 ) Change subject: include/console: Rename POST_ENTRY_RAMSTAGE to POST_ENTRY_HARDWAREMAIN ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Gerrit-Change-Number: 52947 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 16:53:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Sumeet R Pawnikar (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52859 to look at the new patch set (#2). Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... mb/google/brya: enable DPTF functionality for brya Enable DPTF functionality for Alder Lake based brya BRANCH=None BUG=None TEST=Built and tested on brya board Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52859/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: enable DPTF functionality for brya
by Sumeet R Pawnikar (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52859 ) Change subject: mb/google/brya: enable DPTF functionality for brya ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/52859/comment/91a01bb1_4fa0240c PS1, Line 123: chip drivers/intel/dptf > Hi Sumeet, having gone through 2 programs with this approach (volteer & dedede), I think I'd like to […] Thanks Tim for this information. With this, it makes sense to keep those DPTF parameters in each overridetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/52859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Gerrit-Change-Number: 52859 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 16:49:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional
by EricR Lai (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Ian Feng, Vitaly Rodionov, Angel Pons, Marco Chen, Karthik Ramasubramanian. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52981 ) Change subject: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/cs42l42/chip.h: https://review.coreboot.org/c/coreboot/+/52981/comment/a51ebf11_e0f535e8 PS2, Line 118: * Default = true > Where is this default enforced? it kernel driver https://patchwork.kernel.org/project/alsa-devel/patch/20210507141748.742037… -- To view, visit https://review.coreboot.org/c/coreboot/+/52981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea Gerrit-Change-Number: 52981 Gerrit-PatchSet: 2 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 16:48:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Ian Feng, Vitaly Rodionov, Marco Chen, Karthik Ramasubramanian, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52981 ) Change subject: drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/cs42l42/chip.h: https://review.coreboot.org/c/coreboot/+/52981/comment/829ea5fe_6b7f7be8 PS2, Line 118: * Default = true Where is this default enforced? -- To view, visit https://review.coreboot.org/c/coreboot/+/52981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87c6f01af1bdb5b1cb8e399191519598d7fbe9ea Gerrit-Change-Number: 52981 Gerrit-PatchSet: 2 Gerrit-Owner: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Vitaly Rodionov <vitaly.rodionov(a)cirrus.corp-partner.google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 07 May 2021 16:47:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: include/console: Fix duplicate entry of postcode 0x79
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Subrata Banik, Nico Huber, Furquan Shaikh, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52895 ) Change subject: include/console: Fix duplicate entry of postcode 0x79 ...................................................................... Patch Set 4: (1 comment) File src/include/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/52895/comment/0a323922_2e0a545d PS3, Line 190: POST_BS_WRITE_TABLES > Ah, macros... Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Gerrit-Change-Number: 52895 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Fri, 07 May 2021 16:45:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subi.banik(a)gmail.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2021