coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call
by Raul Rangel (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53921 ) Change subject: soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cf50257d767525d682602cdcc5547bf001fe2ac Gerrit-Change-Number: 53921 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 18:27:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution
by Michał Żygowski (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52762 ) Change subject: cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution ...................................................................... Patch Set 4: (1 comment) File src/cpu/amd/pi/00730F01/model_16_init.c: https://review.coreboot.org/c/coreboot/+/52762/comment/ef26b661_6a64523e PS4, Line 28: /* > family 14h has a acpi_is_wakeup_s3 check in here to either do this or call restore_mtrr; not sure if […] Since apu2 is the only platform using this, there is no need for that, because apu2 does not support ACPI resume. Moreover S3 is known to be broken on binaryPI. -- To view, visit https://review.coreboot.org/c/coreboot/+/52762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2d7a75affd7d3d3a1bc6327fb423e206b28562f Gerrit-Change-Number: 52762 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 18:27:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common
by Raul Rangel (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53920 ) Change subject: soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446 Gerrit-Change-Number: 53920 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 18:27:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions
by Michał Żygowski (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Krystian Hebel, Kyösti Mälkki, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52926 ) Change subject: nb/amd/pi/00730F01/northbridge.c: Use generic allocation functions ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > didn't spot anything that looked obviously wrong and since it has 100% test coverage, i'm confident […] It basically changes nothing, except the order the code is executed. Without the patch, the memory ranges were discovered during setting resources phase and marked as usable. Now it is done during read resources phase which is correct right? SAme goes for the similar patch for family14. -- To view, visit https://review.coreboot.org/c/coreboot/+/52926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Gerrit-Change-Number: 52926 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 18:22:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/metaknight: Update LTE USB port configuration
by Raymond Wong (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Karthik Ramasubramanian. Raymond Wong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52960 ) Change subject: mb/google/dedede/var/metaknight: Update LTE USB port configuration ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155 Gerrit-Change-Number: 52960 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Raymond Wong <wongraymond(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 18:21:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: Add a variant callback to update devicetree config
by Raymond Wong (Code Review) 07 May '21

07 May '21

Attention is currently required from: David Wu, Henry Sun, Karthik Ramasubramanian. Raymond Wong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52887 ) Change subject: mb/google/dedede: Add a variant callback to update devicetree config ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9 Gerrit-Change-Number: 52887 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Raymond Wong <wongraymond(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 07 May 2021 18:21:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call
by Felix Held (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53921 ) Change subject: soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call ...................................................................... soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call BUG=b:187212773, b:185481298 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2cf50257d767525d682602cdcc5547bf001fe2ac --- M src/soc/amd/cezanne/acpi/soc.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/53921/1 diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index f7781da..5039ca1 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -17,6 +17,8 @@ #include "pci0.asl" } /* End \_SB scope */ +#include <soc/amd/common/acpi/alib.asl> + #include <soc/amd/common/acpi/platform.asl> #include <soc/amd/common/acpi/sleepstates.asl> @@ -30,4 +32,6 @@ */ Method (PNOT) { + /* Report AC/DC state to ALIB using WAL1() */ + \WAL1 () } -- To view, visit https://review.coreboot.org/c/coreboot/+/53921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cf50257d767525d682602cdcc5547bf001fe2ac Gerrit-Change-Number: 53921 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common
by Felix Held (Code Review) 07 May '21

07 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53920 ) Change subject: soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common ...................................................................... soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common TEST=Mandolin still boots into Linux and there's no ACPI warning in dmesg. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446 --- A src/soc/amd/common/acpi/alib.asl M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl 3 files changed, 31 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/53920/1 diff --git a/src/soc/amd/common/acpi/alib.asl b/src/soc/amd/common/acpi/alib.asl new file mode 100644 index 0000000..bf4a137 --- /dev/null +++ b/src/soc/amd/common/acpi/alib.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/alib.h> + +/* The ALIB method object is defined in an SSDT */ +External(\_SB.ALIB, MethodObj) + +/* Wrapper method that calls ALIB function 1 to report current AC/DC state. */ +Method (WAL1) +{ + /* Send ALIB Function 1 the AC/DC state */ + Local0 = Buffer (0x03) {} + CreateWordField (Local0, 0, F1SZ) + CreateByteField (Local0, 2, F1DA) + + /* First argument is size i.e. 3 bytes */ + F1SZ = 3 + + /* + * Second argument is power state i.e. AC or DC. + * ALIB expects AC = 0, DC = 1. + * PWRS reports AC = 1, DC = 0. + * + * Hence, need to invert the state of PWRS. + */ + F1DA = \PWRS ^ 1 + + Printf ("ALIB call: func 1 params %o", Local0) + \_SB.ALIB (ALIB_FUNCTION_REPORT_AC_DC_STATE, Local0) +} diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 869602c..b7395fc 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -1,32 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/alib.h> - -/* - * Wrapper method that calls ALIB function 1 to report current AC/DC state. - */ -Method (WAL1) -{ - /* Send ALIB Function 1 the AC/DC state */ - Local0 = Buffer (0x03) {} - CreateWordField (Local0, 0, F1SZ) - CreateByteField (Local0, 2, F1DA) - - /* First argument is size i.e. 3 bytes */ - F1SZ = 3 - - /* - * Second argument is power state i.e. AC or DC. - * ALIB expects AC = 0, DC = 1. - * PWRS reports AC = 1, DC = 0. - * - * Hence, need to invert the state of PWRS. - */ - F1DA = \PWRS ^ 1 - - Printf ("ALIB call: func 1 params %o", Local0) - \_SB.ALIB (ALIB_FUNCTION_REPORT_AC_DC_STATE, Local0) -} +#include <soc/amd/common/acpi/alib.asl> Method (PNOT) { diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 0b253c9..e948bca 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -2,8 +2,6 @@ #include <arch/ioapic.h> -External(\_SB.ALIB, MethodObj) - /* System Bus */ /* _SB.PCI0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446 Gerrit-Change-Number: 53920 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Michał Żygowski (Code Review) 07 May '21

07 May '21

Attention is currently required from: Nico Huber, Angel Pons, Kyösti Mälkki, Felix Held. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... Patch Set 2: (4 comments) File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52935/comment/01df3454_4511ebf7 PS2, Line 275: * 0xc0000 - 0xcffff: VGA OPROM > same comment about the d segment here * 0xd0000 - 0xfffff: SeaBIOS, if used If I am correct. D segment is used for oproms anyway. https://review.coreboot.org/c/coreboot/+/52935/comment/cd75ea36_32a6e44e PS2, Line 289: resource_t > unsigned long why not resource_t? https://review.coreboot.org/c/coreboot/+/52935/comment/3d860fa9_08d1f303 PS2, Line 382: // 4 1T > What does this comment mean? No idea, it was just there before. May remove actually https://review.coreboot.org/c/coreboot/+/52935/comment/ded33f95_638f5420 PS2, Line 382: resource_t > unsigned long Why? What is the policy behind using resource_t anyway? -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 18:19:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer: increase CBFS_MCACHE_SIZE
by Nick Vaccaro (Code Review) 07 May '21

07 May '21

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53919 ) Change subject: mb/google/volteer: increase CBFS_MCACHE_SIZE ...................................................................... mb/google/volteer: increase CBFS_MCACHE_SIZE Increase CBFS_MCACHE_SIZE for all volteer variants. BUG=b:187095474 TEST="test_that --board=volteer --autotest_dir=/mnt/host/source/src/third_party/autotest/files $DUT_IP firmware_CbfsMcache" and verify it passes on volteer2. Change-Id: I04604395d41b878e7ef53aadcb27140c203a579e Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/53919/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index bdfb6da..7328cdb 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -37,6 +37,14 @@ if BOARD_GOOGLE_BASEBOARD_VOLTEER +config CBFS_MCACHE_RW_PERCENTAGE + int + default 50 + +config CBFS_MCACHE_SIZE + hex + default 0x4000 + config CHROMEOS select CHROMEOS_CSE_BOARD_RESET_OVERRIDE select CHROMEOS_DRAM_PART_NUMBER_IN_CBI -- To view, visit https://review.coreboot.org/c/coreboot/+/53919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04604395d41b878e7ef53aadcb27140c203a579e Gerrit-Change-Number: 53919 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021