Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53924 )
Change subject: doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
......................................................................
Patch Set 1: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/53924
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6
Gerrit-Change-Number: 53924
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Fri, 07 May 2021 19:38:51 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Christian Walter, Stefan Reinauer, David Hendricks, Angel Pons, Subrata Banik, ron minnich.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52735 )
Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change
......................................................................
Patch Set 2:
(3 comments)
File Documentation/releases/coreboot-4.14-relnotes.md:
https://review.coreboot.org/c/coreboot/+/52735/comment/ec78225d_a792bf41
PS2, Line 67: soc
We generally write SoC, any reason not to do this here?
https://review.coreboot.org/c/coreboot/+/52735/comment/bc4339b8_bc219af8
PS2, Line 76: https://www.intel.in/content/www/in/en/products/details/processors/xeon/sca…
nit: Does Intel have a locale neutral URL scheme so that readers end up on a server close to them and their preferred language (if available)? Couldn't find one quickly.
https://review.coreboot.org/c/coreboot/+/52735/comment/7ac6180b_6f16c2a0
PS2, Line 78: https://doc.coreboot.org/mainboard/ocp/tiogapass.html
That's an internal link, so should be possible to state as ../mainboard/ocp/tiogapass.md. Advantage: When users render their own documentation, the link still points to their own instance.
--
To view, visit https://review.coreboot.org/c/coreboot/+/52735
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e
Gerrit-Change-Number: 52735
Gerrit-PatchSet: 2
Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com>
Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com>
Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com>
Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Attention: ron minnich <rminnich(a)gmail.com>
Gerrit-Comment-Date: Fri, 07 May 2021 19:38:30 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Felix Singer, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53925 )
Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree
......................................................................
Patch Set 1: Code-Review+1
--
To view, visit https://review.coreboot.org/c/coreboot/+/53925
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862
Gerrit-Change-Number: 53925
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Comment-Date: Fri, 07 May 2021 19:29:41 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53925 )
Change subject: soc/intel/skylake: Set proper defaults in chipset devicetree
......................................................................
soc/intel/skylake: Set proper defaults in chipset devicetree
LPC, P2SB and Power Management controller are always needed. Thus,
enable them by default.
Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/soc/intel/skylake/chipset.cb
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/53925/1
diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
index 428db67..37100f0 100644
--- a/src/soc/intel/skylake/chipset.cb
+++ b/src/soc/intel/skylake/chipset.cb
@@ -59,9 +59,9 @@
device pci 1e.4 alias emmc off end # EMMC
device pci 1e.5 alias sdio off end # SDIO
device pci 1e.6 alias sdxc off end # SDXC
- device pci 1f.0 alias lpc_espi off end # LPC Interface
- device pci 1f.1 alias p2sb off end # P2SB
- device pci 1f.2 alias pmc off end # Power Management Controller
+ device pci 1f.0 alias lpc_espi on end # LPC Interface
+ device pci 1f.1 alias p2sb on end # P2SB
+ device pci 1f.2 alias pmc on end # Power Management Controller
device pci 1f.3 alias hda off end # Intel HDA
device pci 1f.4 alias smbus off end # SMBus
device pci 1f.5 alias fast_spi off end # PCH SPI
--
To view, visit https://review.coreboot.org/c/coreboot/+/53925
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862
Gerrit-Change-Number: 53925
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net>
Gerrit-MessageType: newchange
Attention is currently required from: Lance Zhao, Shaunak Saha, Nico Huber, Furquan Shaikh, Wonkyu Kim, Matt DeVillier, Ravishankar Sarawadi, Srinidhi N Kaushik, Subrata Banik.
Patrick Georgi has uploaded a new patch set (#4) to the change originally created by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/52696 )
Change subject: *x86: fix x2apic mode boot issue
......................................................................
*x86: fix x2apic mode boot issue
Fix booting issues on google/kahlee introduced by CB:51723.
Update use inital apic id in smm_stub.S to support xapic mode error.
Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode.
TEST=Boot to OS and check apicid, debug log for CPUIDs
cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc
Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com>
Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37
---
M src/cpu/x86/smm/smm_stub.S
M src/include/cpu/x86/lapic.h
M src/include/cpu/x86/lapic_def.h
3 files changed, 22 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/52696/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/52696
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37
Gerrit-Change-Number: 52696
Gerrit-PatchSet: 4
Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lance Zhao
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Lance Zhao
Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-Attention: Nico Huber <nico.h(a)gmx.de>
Gerrit-Attention: Furquan Shaikh <furquan(a)google.com>
Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>
Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com>
Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com>
Gerrit-MessageType: newpatchset
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53924 )
Change subject: doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
......................................................................
doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6
---
M Documentation/releases/coreboot-4.14-relnotes.md
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/53924/1
diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
index e383c2e..6b629f4 100644
--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -52,4 +52,13 @@
Significant changes
-------------------
+### AMD SoC cleanup and initial Cezanne APU support
+
+There's initial support for the AMD Cezanne APUs in the tree. This code
+hasn't started as a copy of the previous generation, but was based on a
+slightly modified version of the example/min86 SoC. During the cleanup
+of the existing Picasso SoC code the common parts of the code were
+moved to the common AMD SoC code, so that they could be used by the
+Cezanne code instead of adding another slightly different copy.
+
### Add significant changes here
--
To view, visit https://review.coreboot.org/c/coreboot/+/53924
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6
Gerrit-Change-Number: 53924
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange