coreboot-gerrit May 2021

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Change in coreboot[master]: doc/relnotes/4.14: add Intel Xeon-SP support status change
by Jonathan Zhang (Code Review) 07 May '21

07 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Christian Walter, Stefan Reinauer, David Hendricks, Angel Pons, Subrata Banik, ron minnich. Hello build bot (Jenkins), Marc Jones, Anjaneya "Reddy" Chagam, Stefan Reinauer, Christian Walter, David Hendricks, Angel Pons, Subrata Banik, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52735 to look at the new patch set (#3). Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change ...................................................................... doc/relnotes/4.14: add Intel Xeon-SP support status change Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e --- M Documentation/releases/coreboot-4.14-relnotes.md 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52735/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Gerrit-Change-Number: 52735 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: adjust the size for RO/RW mcache
by Julius Werner (Code Review) 07 May '21

07 May '21

Attention is currently required from: Furquan Shaikh, Nick Vaccaro, Zhuohao Lee. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53908 ) Change subject: mb/google/volteer: adjust the size for RO/RW mcache ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Maybe the best course of action is just to remove the global RW_PERCENTAGE default for Chrome OS (make it always default to 50) and globally increase the MCACHE_SIZE default for x86 to 16K. I just made the current values up and clearly my assumptions were not quite realistic. For the RW asset override I'm still kinda hoping that'll remain a rare exception, but on the other hand this size is not something we can increase after RO has been frozen so it's probably safer to always anticipate it just in case. As long as we have the CAR space available, there's no reason not to use it. -- To view, visit https://review.coreboot.org/c/coreboot/+/53908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8 Gerrit-Change-Number: 53908 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 21:03:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: doc/relnotes/4.14: add Intel Xeon-SP support status change
by Jonathan Zhang (Code Review) 07 May '21

07 May '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Christian Walter, Stefan Reinauer, David Hendricks, Angel Pons, Subrata Banik, ron minnich. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52735 ) Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change ...................................................................... Patch Set 2: (3 comments) File Documentation/releases/coreboot-4.14-relnotes.md: https://review.coreboot.org/c/coreboot/+/52735/comment/f8bb67de_c3096e17 PS2, Line 67: soc > We generally write SoC, any reason not to do this here? Ack https://review.coreboot.org/c/coreboot/+/52735/comment/b116a1d1_9b909034 PS2, Line 76: https://www.intel.in/content/www/in/en/products/details/processors/xeon/sca… > nit: Does Intel have a locale neutral URL scheme so that readers end up on a server close to them an […] Sorry I am not able to find the local neutral URL scheme. That being said, user can go to top right corner and change locale. https://review.coreboot.org/c/coreboot/+/52735/comment/642a2f2f_da90bab6 PS2, Line 78: https://doc.coreboot.org/mainboard/ocp/tiogapass.html > That's an internal link, so should be possible to state as ../mainboard/ocp/tiogapass.md. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e Gerrit-Change-Number: 52735 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 07 May 2021 21:02:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: skylake mainboards: Use enum values for SaGv
by Angel Pons (Code Review) 07 May '21

07 May '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52098 ) Change subject: skylake mainboards: Use enum values for SaGv ...................................................................... skylake mainboards: Use enum values for SaGv Replace `3` with `SaGv_Enabled`, which has the same value. Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb 11 files changed, 11 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c0531fa..07b9100 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -45,7 +45,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index e9d5a35..d33c9fd 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -76,7 +76,7 @@ register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 5a48c5d..3f7ce89 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -44,7 +44,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d3e351a..e779ae4 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -52,7 +52,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 09bdac4..c5d8539 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -40,7 +40,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 25d720e..885fcbd 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -39,7 +39,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 6eb83ac..3c7930d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -40,7 +40,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 39e241e..2b7debd 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -45,7 +45,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 05f62e7..4ea4740 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -52,7 +52,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index ac8fbc9..df571aa 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -40,7 +40,7 @@ register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 47a9a5c..84efd6a 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -54,7 +54,7 @@ register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" - register "SaGv" = "3" + register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms -- To view, visit https://review.coreboot.org/c/coreboot/+/52098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3 Gerrit-Change-Number: 52098 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: skylake DT/HALO mainboards: Drop `SaGv` setting
by Angel Pons (Code Review) 07 May '21

07 May '21

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52097 ) Change subject: skylake DT/HALO mainboards: Drop `SaGv` setting ...................................................................... skylake DT/HALO mainboards: Drop `SaGv` setting SaGv is only supported on ULT/ULX hardware. Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52097 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 3 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 74e5720..0acba3a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -19,7 +19,6 @@ # FSP Configuration register "PrimaryDisplay" = "Display_PEG" - register "SaGv" = "SaGv_Enabled" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index d049db1..44ff902 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -20,8 +20,6 @@ register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" - register "SaGv" = "SaGv_Enabled" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "0x02" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 76aec3f..1196629 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -2,7 +2,6 @@ # FSP Configuration register "SkipExtGfxScan" = "1" - register "SaGv" = "SaGv_Disabled" # SATA configuration register "SataSalpSupport" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/52097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b Gerrit-Change-Number: 52097 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: aopen/dxplplusu: Add early GPIO settings
by Angel Pons (Code Review) 07 May '21

07 May '21

Attention is currently required from: Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52815 ) Change subject: aopen/dxplplusu: Add early GPIO settings ...................................................................... Patch Set 1: (1 comment) File src/mainboard/aopen/dxplplusu/bootblock.c: https://review.coreboot.org/c/coreboot/+/52815/comment/db34091f_69e01f51 PS1, Line 13: #define PME_BASE 0xe00 > Do we account for PNP fixed IO's in read_resources? This does fall into into the 0x0-0x1000 IO regio […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib211e9c4b487fadec3d3487f9d745f44d8ca4579 Gerrit-Change-Number: 52815 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 07 May 2021 20:31:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Fix typo
by Kyösti Mälkki (Code Review) 07 May '21

07 May '21

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53926 ) Change subject: cpu/x86/smm: Fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28f262078cf7f5ec4ed707639e845710a8cc56ea Gerrit-Change-Number: 53926 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 07 May 2021 20:17:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/spd_cache-test test case
by Paul Fagerburg (Code Review) 07 May '21

07 May '21

Attention is currently required from: Jakub Czapiga, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52938 ) Change subject: tests: Add lib/spd_cache-test test case ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75 Gerrit-Change-Number: 52938 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Fri, 07 May 2021 20:14:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
by Kyösti Mälkki (Code Review) 07 May '21

07 May '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53924 ) Change subject: doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/53924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6 Gerrit-Change-Number: 53924 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 20:08:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: *x86: fix x2apic mode boot issue
by Patrick Georgi (Code Review) 07 May '21

07 May '21

Attention is currently required from: Lance Zhao, Shaunak Saha, Nico Huber, Furquan Shaikh, Wonkyu Kim, Matt DeVillier, Ravishankar Sarawadi, Srinidhi N Kaushik, Subrata Banik. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52696 ) Change subject: *x86: fix x2apic mode boot issue ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37 Gerrit-Change-Number: 52696 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Comment-Date: Fri, 07 May 2021 20:06:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021