coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Julius Werner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Vinod Polimera, Douglas Anderson. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52959 ) Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... Patch Set 4: (3 comments) File src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c: https://review.coreboot.org/c/coreboot/+/52959/comment/f7530189_54e3db3f PS4, Line 189: [I2C_RAW_WRITE] = I2C_OVER_AUX_WRITE_MOT_1, : [I2C_RAW_READ] = I2C_OVER_AUX_READ_MOT_1, > I haven't fully analyzed the side effects, but I _think_ that always using MOT=1 here isn't quite ri […] Oh, cool, now I actually understand what MOT means. Couldn't find it explained in the datasheet. But you're right, upon closer inspection it does ask you to use a different command code for the last transfer. https://review.coreboot.org/c/coreboot/+/52959/comment/7b55787d_40064bdb PS4, Line 200: i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd[request] << 4)) > I don't know if it maters, but kernel driver and datasheet show doing this _first_, before the setti […] Done https://review.coreboot.org/c/coreboot/+/52959/comment/f5c78749_da9361ca PS4, Line 220: > In the kernel driver, we check a whole bunch of extra status things here (timeout, short, and failed […] *sigh*... I knew I was making a mistake when I decided to "quickly" write this myself instead of punting it off to Qualcomm. ^^ Okay, fine. Error handling added. -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Douglas Anderson <dianders(a)chromium.org> Gerrit-Comment-Date: Fri, 07 May 2021 22:36:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Douglas Anderson <dianders(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/sn65dsi86: Switch EDID reading to use "indirect mode"
by Julius Werner (Code Review) 08 May '21

08 May '21

Attention is currently required from: Vinod Polimera, Julius Werner. Hello Vinod Polimera, build bot (Jenkins), Douglas Anderson, Xuxin Xiong, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52959 to look at the new patch set (#5). Change subject: drivers/sn65dsi86: Switch EDID reading to use "indirect mode" ...................................................................... drivers/sn65dsi86: Switch EDID reading to use "indirect mode" The SN65DSI86 eDP bridge supports two ways to read the EDID: for now we've been using "direct mode", which works by basically making the bridge I2C device listen to another chip address besides its own and proxy all requests received there directly to the eDP AUX channel. The great part about that mode is that it is super easy and hassle-free to use. The not so great part about it is that it doesn't work: for EDID extensions, the last byte (which happens to contain the checksum) is somehow always read as zero. We presume this is a hardware bug in the bridge part. The other, much more annoying way is "indirect mode", where each byte transmitted over the AUX channel has to be manually set up in the I2C registers of the bridge, just like we're already doing with DPCD transactions. Thankfully, we can reuse most of the DPCD code for this so it's not a lot of extra code. It's a bit slower but not as much as you'd expect (26ms instead of 18ms on my board), and the difference is not very relevant compared to common total times for display init. Also, some of the (previously unused) enum definitions for the AUX_CMD mode field of the bridge had just been plain wrong for some reason, and needed to be fixed to make this work. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 139 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52959/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Gerrit-Change-Number: 52959 Gerrit-PatchSet: 5 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/cezanne: Enable GNB IO-APIC _PRT
by Raul Rangel (Code Review) 08 May '21

08 May '21

1 0

Change in coreboot[master]: soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/53935 ) Change subject: soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT ...................................................................... soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT We can now delete the picasso specific version. BUG=b:184766519 TEST=Build zork and verify SSDT has not changed Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f --- M src/soc/amd/picasso/pcie_gpp.c 1 file changed, 1 insertion(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/53935/1 diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 15174f6..eabaa77 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -60,68 +60,6 @@ return NULL; } -static void acpigen_write_PRT(const struct device *dev) -{ - char link_template[] = "\\_SB.INTX"; - unsigned int irq_index; - - const struct pci_routing_info *pci_routing = get_pci_routing_info(dev->path.pci.devfn); - if (!pci_routing) { - printk(BIOS_ERR, "PCI routing table not found for %s\n", dev_path(dev)); - return; - } - - acpigen_write_method("_PRT", 0); - - /* If (PICM) */ - acpigen_write_if(); - acpigen_emit_namestring("PICM"); - - /* Return (Package{...}) */ - acpigen_emit_byte(RETURN_OP); - - acpigen_write_package(4); /* Package - APIC Routing */ - for (unsigned int i = 0; i < 4; ++i) { - irq_index = pci_calculate_irq(pci_routing, i); - - acpigen_write_package(4); - /* There is only one device attached to the bridge */ - acpigen_write_dword(0x0000FFFF); - acpigen_write_byte(i); - acpigen_write_byte(0); /* Source: GSI */ - /* GNB IO-APIC is located after the FCH IO-APIC */ - acpigen_write_dword(IO_APIC_INTERRUPTS + irq_index); - acpigen_pop_len(); - } - acpigen_pop_len(); /* Package - APIC Routing */ - - /* Else */ - acpigen_write_else(); - - /* Return (Package{...}) */ - acpigen_emit_byte(RETURN_OP); - - acpigen_write_package(4); /* Package - PIC Routing */ - for (unsigned int i = 0; i < 4; ++i) { - irq_index = pci_calculate_irq(pci_routing, i); - - link_template[8] = 'A' + (irq_index % 8); - - acpigen_write_package(4); - /* There is only one device attached to the bridge */ - acpigen_write_dword(0x0000FFFF); - acpigen_write_byte(i); - acpigen_emit_namestring(link_template); - acpigen_write_dword(0); - acpigen_pop_len(); - } - acpigen_pop_len(); /* Package - PIC Routing */ - - acpigen_pop_len(); /* End Else */ - - acpigen_pop_len(); /* Method */ -} - /* * This function writes a PCI device with _ADR, _STA, and _PRT objects: * Example: @@ -230,7 +168,7 @@ acpigen_write_ADR_pci_device(dev); acpigen_write_STA(acpi_device_status(dev)); - acpigen_write_PRT(dev); + acpigen_write_pci_GNB_PRT(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/53935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f Gerrit-Change-Number: 53935 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/cezanne: Generate PCI routing table
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51556 to look at the new patch set (#7). Change subject: soc/amd/cezanne: Generate PCI routing table ...................................................................... soc/amd/cezanne: Generate PCI routing table Use the new acpigen_write_PRT to write the _PRT for each PCI bridge. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 --- M src/soc/amd/cezanne/acpi/soc.asl M src/soc/amd/cezanne/pcie_gpp.c 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/51556/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/cezanne: add GNB IOAPIC support
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Raul Rangel has uploaded a new patch set (#3) to the change originally created by Felix Held. ( https://review.coreboot.org/c/coreboot/+/52905 ) Change subject: soc/amd/cezanne: add GNB IOAPIC support ...................................................................... soc/amd/cezanne: add GNB IOAPIC support To configure and enable the IOAPIC in the graphics and northbridge (GNB) container, FSP needs to write an undocumented register, so pass the GNB IOAPIC MMIO base address to make it show up at that address. BUG=b:187083211 TEST=Boot guybrush and see IO-APIC initialized IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23 IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/root_complex.c 4 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52905/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e Gerrit-Change-Number: 52905 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52911 ) Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ...................................................................... Patch Set 4: (3 comments) File src/soc/amd/common/fsp/pci/pci_routing_info.c: https://review.coreboot.org/c/coreboot/+/52911/comment/cd3bfd2e_01e69d7d PS3, Line 44: sizeof(*routing_table) > sizeof(pci_routing_info) should also work and i'd find that a bit easier to read Done https://review.coreboot.org/c/coreboot/+/52911/comment/a137a08c_67ff8017 PS3, Line 76: > > this should probably be a >= and not a >, since ARRAY_SIZE(pcie_swizzle_table) is 4, but the maximum […] Good catch! https://review.coreboot.org/c/coreboot/+/52911/comment/ba26aaa3_6b4052f5 PS3, Line 79: > > probably same here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Gerrit-Change-Number: 52911 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 22:35:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52911 to look at the new patch set (#4). Change subject: soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table ...................................................................... soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table These are helper methods for interacting with the AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID. BUG=b:184766519, b:184766197 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 --- A src/soc/amd/common/fsp/pci/Kconfig A src/soc/amd/common/fsp/pci/Makefile.inc A src/soc/amd/common/fsp/pci/pci_routing_info.c 3 files changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/52911/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923 Gerrit-Change-Number: 52911 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52917 ) Change subject: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/common/fsp/pci/acpi_prt.c: https://review.coreboot.org/c/coreboot/+/52917/comment/bb6c9b58_9eb5c78c PS3, Line 22: acpigen_write_PRT_source_entry > acpigen_write_PRT_GSI_entry lol, I caught that when I finally enabled the GNB IO-APIC. -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 07 May 2021 22:35:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT
by Raul Rangel (Code Review) 08 May '21

08 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52917 to look at the new patch set (#4). Change subject: soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT ...................................................................... soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT This is loosely based off of picasso/pcie_gpp.c. This version uses the acpigen_write_PRT_X methods to write the actual records. There are also two functions, 1 for using the GNB, and one for using the FCH. The FCH one is useful when the GNB IO-APIC has not been initialized. BUG=b:184766519 TEST=Dump guybrush ACPI and verify it looks correct Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/block/pci/Makefile.inc A src/soc/amd/common/block/pci/acpi_prt.c 3 files changed, 217 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/52917/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76 Gerrit-Change-Number: 52917 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021